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WBNOINVD
WBNOINVD — Write Back and Do Not Invalidate Cache
Opcode / Instruction | Op/ En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
F3 0F 09 WBNOINVD | A | V/V | WBNOINVD | Write back and do not flush internal caches; initiate writing-back without flushing of external caches. |
Op/En | Tuple | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
A | NA | NA | NA | NA | NA |
The WBNOINVD instruction writes back all modified cache lines in the processor’s internal cache to main memory but does not invalidate (flush) the internal caches.
After executing this instruction, the processor does not wait for the external caches to complete their write-back operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache write-back signal. The amount of time or cycles for WBNOINVD to complete will vary due to size and other factors of different cache hierarchies. As a consequence, the use of the WBNOINVD instruction can have an impact on logical processor interrupt/event response time.
The WBNOINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see “Serializing Instructions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
The WBNOINVD instruction is implementation dependent, and its function may be implemented differently on future Intel 64 and IA-32 processors.
WriteBack(InternalCaches);
Continue; (* Continue execution *)
WBNOINVD void _wbnoinvd(void);
None.
#GP(0) If the current privilege level is not 0.
#UD If the LOCK prefix is used.
#UD If the LOCK prefix is used.
#GP(0) WBNOINVD cannot be executed at the virtual-8086 mode.
Same exceptions as in protected mode.
Same exceptions as in protected mode.
Source: Intel® Architecture Instruction Set Extensions and Future Features Programming Reference (May 2019)
Generated: 28-5-2019