CHIPS Alliance

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110 repositories

website-experiments
Public
HTML
•1•0•0•0•Updated Jan 2, 2025Jan 2, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•1•5•0•0•Updated Jan 2, 2025Jan 2, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•75•305•46•23•Updated Jan 1, 2025Jan 1, 2025
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•76•254•21•10•Updated Jan 1, 2025Jan 1, 2025
t1
Public
Scala
•
Apache License 2.0
•23•125•16•26•Updated Jan 1, 2025Jan 1, 2025
caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•46•98•109•56•Updated Jan 1, 2025Jan 1, 2025
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•1•5•2•2•Updated Jan 1, 2025Jan 1, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•3•8•13•4•Updated Dec 31, 2024Dec 31, 2024
chisel
Public
Chisel: A Modern Hardware Design Language
chip-generator chisel rtl chisel3 firrtl scala verilog
Scala
•
Apache License 2.0
•609•4.1k•316•165•Updated Dec 31, 2024Dec 31, 2024
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•3•10•1•0•Updated Dec 30, 2024Dec 30, 2024
rocket-pcb
Public
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Verilog
•
Apache License 2.0
•2•7•0•1•Updated Dec 29, 2024Dec 29, 2024
synlig
Public
SystemVerilog synthesis tool
Verilog
•
Apache License 2.0
•23•176•69•10•Updated Dec 26, 2024Dec 26, 2024
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
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Apache License 2.0
•20•68•5•0•Updated Dec 25, 2024Dec 25, 2024
verible
Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
productivity analysis style-linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server
C++
•
Other
•217•1.4k•475•21•Updated Dec 24, 2024Dec 24, 2024
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•28•47•25•16•Updated Dec 24, 2024Dec 24, 2024
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•41•79•74•14•Updated Dec 23, 2024Dec 23, 2024
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•2•13•10•2•Updated Dec 23, 2024Dec 23, 2024
rvdecoderdb
Public
The Scala parser to parse riscv/riscv-opcodes generate
Scala
•0•11•0•1•Updated Dec 23, 2024Dec 23, 2024
synlig-logs
Public
SystemVerilog
•0•0•0•0•Updated Dec 23, 2024Dec 23, 2024
systolic
Public
A matrix multiplication implementation via systolic array
Nix
•1•3•0•1•Updated Dec 23, 2024Dec 23, 2024
chips-alliance-website
Public
SCSS
•
MIT License
•5•3•9•8•Updated Dec 21, 2024Dec 21, 2024
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•22•16•10•8•Updated Dec 20, 2024Dec 20, 2024
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•22•6•19•2•Updated Dec 18, 2024Dec 18, 2024
VeeRwolf
Public
FuseSoC-based SoC for VeeR EH1 and EL2
tools fusesoc swerv veer
Verilog
•68•299•21•0•Updated Dec 11, 2024Dec 11, 2024
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•35•246•21•3•Updated Dec 10, 2024Dec 10, 2024
f4pga
Public
FOSS Flow For FPGA
documentation sphinx symbiflow
Python
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Apache License 2.0
•48•364•13•13•Updated Dec 10, 2024Dec 10, 2024
firtool-resolver
Public
Scala
•1•2•0•1•Updated Dec 8, 2024Dec 8, 2024
tilelink
Public
Scala
•8•27•2•4•Updated Dec 8, 2024Dec 8, 2024
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
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Apache License 2.0
•68•376•51•0•Updated Dec 7, 2024Dec 7, 2024
chisel-template
Public template
A template project for beginning new Chisel work
Scala
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The Unlicense
•188•604•12•3•Updated Dec 4, 2024Dec 4, 2024