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Pull requests: chipsalliance/Cores-VeeR-EL2

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Pull requests list

resize iccm ecc signals
#204 opened Jul 5, 2024 by wsipak Loading…
1
remove verible formatter
#203 opened Jul 5, 2024 by wsipak Loading…
1
Include source code in the dashboard
#202 opened Jul 5, 2024 by RRozak • Draft
1
[DNM] tools/riscv-dv: add bitmanip tests
#201 opened Jul 4, 2024 by fkokosinski • Draft
WIP: Extend coverage tests
#200 opened Jul 3, 2024 by kiryk • Draft
2
tools/riscv-dv: add more PMP tests
#199 opened Jul 2, 2024 by fkokosinski Loading…
3
Render docs in Github Pages
#198 opened Jul 1, 2024 by jbylicki Loading…
9
test specifying privilege modes in simulation in riscv-dv
#197 opened Jun 28, 2024 by wsipak • Draft
42
WIP: Fix linter warnings related to undriven nets
#196 opened Jun 28, 2024 by koblonczek Loading…
8
Test instruction buffer debug override
#195 opened Jun 27, 2024 by koblonczek Loading…
23
Prepare for user mode tests
#192 opened Jun 18, 2024 by kiryk Loading…
add a test for user mode
#185 opened Jun 11, 2024 by wsipak Loading…
65
Add JTAG type as a configurable parameter
#152 opened Dec 14, 2023 by robertszczepanski Loading…
6
Implement script to evaluate lint and format compliance
#75 opened Apr 3, 2023 by mczyz-antmicro Loading…
33
Manual fixes of selected issues raised by lint
#74 opened Apr 3, 2023 by mczyz-antmicro • Draft
Remove VERILATOR ifdefs, use updated Verilator
#60 opened Feb 20, 2023 by mkurc-ant Loading…
Allow injecting user synchronization modules
#56 opened Feb 15, 2023 by mkurc-ant Loading…
5
Adds value parsing to text_in_iccm argument
#53 opened Feb 14, 2023 by JohannesKutning Loading…
FuseSoC and Github Linter Action
#4 opened Jun 17, 2020 by wallento Loading…
14
ProTip! What’s not been updated in a month: updated:<2024-06-05.