test specifying privilege modes in simulation in riscv-dv

[wsipak]

This is a draft to test changes in riscv-dv chipsalliance/riscv-dv#984

[github-actions]

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

design/el2_pmp.sv|151|
design/el2_pmp.sv|156|
design/el2_pmp.sv|159|
design/el2_pmp.sv|305|
design/el2_veer.sv|885|
design/el2_veer.sv|889|
design/el2_veer.sv|896|
design/include/el2_def.sv|440|
design/include/el2_def.sv|442|

[github-actions]

Links to coverage and verification reports for this PR (#197) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/