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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

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  3. verible verible Public

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    Flexible Intermediate Representation for RTL

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Repositories

Showing 10 of 97 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 233 Apache-2.0 68 27 16 Updated Jul 3, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 92 Apache-2.0 19 14 12 Updated Jul 3, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 48 Apache-2.0 34 70 50 Updated Jul 3, 2024
  • synlig-logs Public
    chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Jul 3, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 144 Apache-2.0 20 84 13 Updated Jul 3, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 57 Apache-2.0 30 53 5 Updated Jul 3, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Jul 3, 2024
  • f4pga Public

    FOSS Flow For FPGA

    chipsalliance/f4pga’s past year of commit activity
    Python 337 Apache-2.0 45 13 12 Updated Jul 3, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,817 Apache-2.0 575 301 (1 issue needs help) 150 Updated Jul 3, 2024
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 33 LGPL-3.0 561 0 1 Updated Jul 3, 2024
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