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Incorrect bit width of SV signal produced by "read_systemverilog"
#2428
opened Apr 26, 2024 by
YikeZhou
Assert
struct_ranges.size() <= (wire_node->multirange_dimensions.size() / 2)
failed
#2427
opened Apr 26, 2024 by
YikeZhou
"output int" (signed) in SV is translated into "output" (unsigned) in V
#2425
opened Apr 26, 2024 by
YikeZhou
Encountered unhandled typespec in process_typespec_member: '' of type 'array_typespec'
#2424
opened Apr 26, 2024 by
YikeZhou
ERROR: incompatible mix of lookahead and non-lookahead IDs in LHS expression. in yosys
#2378
opened Mar 21, 2024 by
yosyssyn
ERROR: Assert `size >= 1' failed in /root/synlig/synlig/frontends/systemverilog/uhdm_ast.cc:751.
#2377
opened Mar 21, 2024 by
yosyssyn
Property index 0 is greater than the number of properties in file (.btor2)
#2248
opened Jan 2, 2024 by
CrazybinaryLi
Bug with multidimensional vector inside struct with other vector members
#2196
opened Dec 8, 2023 by
sifferman
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