Incorrect bit width of SV signal produced by "read_systemverilog"

[YikeZhou]

Version

Latest release (2024-03-13-d844d8d)
with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

Reproduction Steps

SystemVerilog code ccsds_turbo_enc_paddr_gen.sv:
(Origin: https://github.com/dshekhalev/FEC/blob/main/rtl/ccsds_turbo/enc/ccsds_turbo_enc_paddr_gen.sv)

module ccsds_turbo_enc_paddr_gen(iP);
  parameter int cW = 14;
  typedef logic [cW-1 : 0] ptab_dat_t;
  input  ptab_dat_t iP      [4] ;
endmodule

Command:

yosys -p 'plugin -i systemverilog; read_systemverilog ccsds_turbo_enc_paddr_gen.sv; write_rtlil'

Output:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <[email protected]>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)


-- Running command `plugin -i systemverilog; read_systemverilog ccsds_turbo_enc_paddr_gen.sv; write_rtlil' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file "/tmp/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0303] /tmp/ccsds_turbo_enc_paddr_gen.sv:1:1: Compile module "work@ccsds_turbo_enc_paddr_gen".
[INF:CP0302] Compile class "work@mailbox".
[INF:CP0302] Compile class "work@process".
[INF:CP0302] Compile class "work@semaphore".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /tmp/ccsds_turbo_enc_paddr_gen.sv:1:1: Top level module "work@ccsds_turbo_enc_paddr_gen".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
[INF:UH0707] Elaborating UHDM...
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 5
Generating RTLIL representation for module `\ccsds_turbo_enc_paddr_gen'.

2. Executing RTLIL backend.
Output filename: <stdout>
# Generated by Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)
autoidx 1
attribute \cells_not_processed 1
attribute \src "/tmp/ccsds_turbo_enc_paddr_gen.sv:1.1-5.10"
module \ccsds_turbo_enc_paddr_gen
  parameter \cW 14
  attribute \src "/tmp/ccsds_turbo_enc_paddr_gen.sv:1.34-1.36"
  attribute \wiretype "\\ptab_dat_t"
  wire width 784 input 1 \iP
end

End of script. Logfile hash: 7c8cb5342d, CPU: user 0.07s system 0.01s, MEM: 33.50 MB peak
Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)
Time spent: 80% 2x read_systemverilog (0 sec), 19% 1x plugin (0 sec), ...

The problem is that 784 seems to be the wrong size for iP. I was expecting 56 (cW*4).

wire width 784 input 1 \iP