Synthesis fail for opl3 example

[TarikHamedovic]

Hello,

I am trying to port the OPL3 example to an Olimex GateMate board that uses yosys as the primary synthesis tool, but I am encountering some errors and warnings that I don't know how to fix.
After installing the SystemVerilog plugin and verifying that it works I tried to synthesize the OPL3 SystemVerilog files with the command in the Makefile where VLOG_SRC are the paths to all of the .sv files in the OPL3 repo, PLUGIN_PATH is the path of the systemverilog.so plugin and TOP is the name of the top module.

synth_svlog: $(VLOG_SRC)
	@test -d log || mkdir -p log
	@test -d net || mkdir -p net
	$(YOSYS) -ql log/synth.log -p 'plugin -i $(PLUGIN_PATH); read_systemverilog $(VLOG_SRC); synth_gatemate -top $(TOP) -nomx8 -vlog net/$(TOP)_synth.v'

And I get lots of warning and errors, but here is the output from the terminal:

make synth_svlog
/home/user/FPGA/tools/synlig/out/current/bin/yosys -ql log/synth.log -p 'plugin -i /home/user/FPGA/tools/synlig/build/release/systemverilog-plugin/systemverilog.so; read_systemverilog modules/top_level/src/opl3.sv modules/channels/src/dac_prep.sv modules/channels/src/channels.sv modules/channels/src/control_operators.sv modules/clks/src/clk_div.sv modules/clks/src/reset_sync.sv modules/i2s/src/i2s.sv modules/operator/src/operator.sv modules/operator/src/calc_phase_inc.sv modules/operator/src/calc_rhythm_phase.sv modules/operator/src/phase_generator.sv modules/operator/src/vibrato.sv modules/operator/src/envelope_generator.sv modules/operator/src/ksl_add_rom.sv modules/operator/src/env_rate_counter.sv modules/operator/src/tremolo.sv modules/operator/src/opl3_log_sine_lut.sv modules/operator/src/opl3_exp_lut.sv modules/timers/src/timers.sv modules/timers/src/timer.sv modules/misc/src/afifo.v modules/misc/src/edge_detector.sv modules/misc/src/mem_simple_dual_port_async_read.sv modules/misc/src/mem_simple_dual_port.sv modules/misc/src/mem_multi_bank.sv modules/misc/src/mem_multi_bank_reset.sv modules/misc/src/pipeline_sr.sv modules/misc/src/synchronizer.sv modules/misc/src/leds.sv modules/host_if/src/host_if.sv modules/host_if/src/trick_sw_detection.sv modules/top_level/pkg/opl3_pkg.sv; synth_gatemate -top opl3  -nomx8 -vlog net/opl3 _synth.v'
[NTE:PP0128] /home/user/opl3/fpga/modules/misc/src/synchronizer.sv:16:65: Non ASCII character detected, replaced by space.
[NTE:EL0503] /home/user/opl3/fpga/modules/top_level/src/opl3.sv:44:1: Top level module "work@opl3".
[NTE:EL0503] /home/user/opl3/fpga/modules/i2s/src/i2s.sv:49:1: Top level module "work@i2s".
[NTE:EL0504] Multiple top level modules in design.
[NTE:EL0531] /home/user/opl3/fpga/modules/channels/src/control_operators.sv:62:12: Negative value in instance "[email protected]_operators"
             text:     logic [$clog2(MODULATION_DELAY)-1:0] delay_counter = 0;
             value: INT:-1.
[NTE:EL0531] /home/user/opl3/fpga/modules/i2s/src/i2s.sv:63:12: Negative value in instance "work@i2s"
             text:     logic [$clog2(SCLK_DIV)-1:0] i2s_sclk_counter = 0;
             value: INT:-1.
[NTE:EL0508] Nb Top level modules: 2.
[NTE:EL0509] Max instance depth: 10.
[NTE:EL0510] Nb instances: 127.
[NTE:EL0511] Nb leaf instances: 4.
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 10
/home/user/opl3/fpga/modules/misc/src/mem_multi_bank.sv:66: Warning: Limited support for multirange wires that don't start from 0
Warning: Removing unelaborated module: \pipeline_sr from the design.
Warning: Removing unelaborated module: \synchronizer from the design.
Warning: Removing unelaborated module: \mem_simple_dual_port_async_read from the design.
Warning: Removing unelaborated module: \mem_simple_dual_port from the design.
Warning: Removing unelaborated module: \afifo from the design.
Warning: Removing unelaborated module: \mem_multi_bank from the design.
Warning: Removing unelaborated module: \edge_detector from the design.
Warning: Removing unelaborated module: \clk_div from the design.
Warning: Removing unelaborated module: \envelope_generator from the design.
Warning: Removing unelaborated module: \timers from the design.
Warning: Removing unelaborated module: \trick_sw_detection from the design.
Warning: Removing unelaborated module: \mem_multi_bank_reset from the design.
Warning: Removing unelaborated module: \timer from the design.
Warning: wire '$unnamed_block$0.i' is assigned in a block at /home/user/opl3/fpga/modules/misc/src/mem_simple_dual_port.sv:66.14-66.19.
Warning: wire '$unnamed_block$0.i' is assigned in a block at /home/user/opl3/fpga/modules/misc/src/mem_simple_dual_port.sv:66.32-66.41.
Warning: Replacing memory \dob_array with list of registers. See /home/user/opl3/fpga/modules/misc/src/mem_multi_bank.sv:0
Warning: wire '$unnamed_block$1.i' is assigned in a block at /home/user/opl3/fpga/modules/misc/src/mem_simple_dual_port_async_read.sv:66.14-66.19.
Warning: wire '$unnamed_block$1.i' is assigned in a block at /home/user/opl3/fpga/modules/misc/src/mem_simple_dual_port_async_read.sv:66.32-66.41.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:121: Warning: Range select [55:48] out of bounds on signal `\opl3_reg_wr': Setting all 8 result bits to undef.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:124: Warning: Range select [63:56] out of bounds on signal `\opl3_reg_wr': Setting all 8 result bits to undef.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:126: Warning: Range select [39:32] out of bounds on signal `\opl3_reg_wr': Setting all 8 result bits to undef.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:127: Warning: Range select [31:24] out of bounds on signal `\opl3_reg_wr': Setting all 8 result bits to undef.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:128: Warning: Range [23:16] select out of bounds on signal `\opl3_reg_wr': Setting 6 MSB bits to undef.
/home/user/opl3/fpga/modules/channels/src/control_operators.sv:331: Warning: Range select [111:104] out of bounds on signal `\opl3_reg_wr': Setting all 8 result bits to undef.
Warning: wire '\sample_opl3_r_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\sample_opl3_l_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\sample_valid_opl3_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dob_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dob_p2' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\rand_num' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\hh_phase_friend' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\modulation_shifted_p3' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\modulation_p2' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\env_p5' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\env_p4' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\tmp_ws7_p5' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\log_sin_plus_gain_p6' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\log_sin_plus_gain_p5' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\is_odd_period_p6' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\is_odd_period_p5' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\is_odd_period_p4' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\is_odd_period_p3' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\prev_final_phase_msb_p4' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\prev_final_phase_msb_p3' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\final_phase_p5' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\final_phase_p4' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\phase_acc_p3' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dam_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\tremolo_index_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\key_on_pulse_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\effective_rate_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\state' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\ksl_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\tmp0_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\rom_out_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\env_int_p2' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\env_int_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\state_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dvb_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\fnum_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\vibrato_index_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\multiplier_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\post_mult_p2' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\pre_mult_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\in_r1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\in_r0' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\hh' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\tc' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\tom' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\sd' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\bd' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dam' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\dvb' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\nts' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\ryt_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\connection_sel_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\modulation_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\use_feedback_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\op_num_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\bank_num_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\delay_counter' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\ryt' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\is_new' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\connection_sel' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\channel_valid' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\channel_r' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\channel_l' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\counter' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\sync_regs' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\host_status_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\wr_p2' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\din_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\address_p1' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\wr_p1_n' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\cs_p1_n' is assigned in a block at /home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\r2' is assigned in a block at modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\r1' is assigned in a block at modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
Warning: wire '\r0' is assigned in a block at modules/top_level/pkg/opl3_pkg.sv:0.0-0.0.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\sample_opl3_r_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\sample_opl3_l_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\sample_valid_opl3_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dob_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dob_p2' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\rand_num' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\hh_phase_friend' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\modulation_shifted_p3' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\modulation_p2' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\env_p5' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\env_p4' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\tmp_ws7_p5' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\log_sin_plus_gain_p6' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\log_sin_plus_gain_p5' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\is_odd_period_p6' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\is_odd_period_p5' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\is_odd_period_p4' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\is_odd_period_p3' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\prev_final_phase_msb_p4' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\prev_final_phase_msb_p3' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\final_phase_p5' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\final_phase_p4' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\phase_acc_p3' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dam_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\tremolo_index_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\key_on_pulse_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\effective_rate_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\state' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\ksl_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\tmp0_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\rom_out_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\env_int_p2' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\env_int_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\state_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dvb_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\fnum_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\vibrato_index_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\multiplier_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\post_mult_p2' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\pre_mult_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\in_r1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\in_r0' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\hh' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\tc' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\tom' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\sd' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\bd' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dam' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\dvb' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\nts' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\ryt_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\connection_sel_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\modulation_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\use_feedback_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\op_num_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\bank_num_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\delay_counter' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\ryt' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\is_new' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\connection_sel' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\channel_valid' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\channel_r' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\channel_l' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\counter' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\sync_regs' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\host_status_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\wr_p2' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\din_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\address_p1' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\wr_p1_n' is implicitly declared.
/home/user/opl3/fpga/modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\cs_p1_n' is implicitly declared.
modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\r2' is implicitly declared.
modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\r1' is implicitly declared.
modules/top_level/pkg/opl3_pkg.sv:0: Warning: Identifier `\r0' is implicitly declared.
/home/user/opl3/fpga/modules/misc/src/mem_simple_dual_port.sv:79: Warning: Identifier `\DEFAULT_VALUE' is implicitly declared.
/home/user/opl3/fpga/modules/misc/src/mem_multi_bank_reset.sv:75: Warning: Identifier `\IDLE' is implicitly declared.
/home/user/opl3/fpga/modules/operator/src/envelope_generator.sv:82: Warning: Identifier `\RELEASE' is implicitly declared.
/home/user/opl3/fpga/modules/channels/src/channels.sv:151: ERROR: Don't know how to detect sign and width for AST_STRUCT node!

What is the issue here?

Thank you in advance.

[chili-chips-ba]

chili-chips-ba/openCologne#3 (comment)
gtaylormb/opl3_fpga#44 - @gtaylormb

[chili-chips-ba]

@kamilrakoczy , @tgorochowik how come the basic package import is not functional?!

This is about GateMate FPGA from CologneChip, where Yosys is the first and only option for synthesis. They are therefore in a unique situation, and this question is not about nice-to-have, but the matter of To-be-or-Not-to-be.