Sol-1: A CPU/Computer System made from 74 series logic.
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Updated
Jul 6, 2024 - C
Sol-1: A CPU/Computer System made from 74 series logic.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilator open-source SystemVerilog simulator and lint system
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
RISC-V Linux SoC, marchID: 0x2b
📚This repository consists of some LeetCode problem solutions.
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Test suite designed to check compliance with the SystemVerilog standard.
SystemVerilog compiler and language services
HDL libraries and projects
Haskell to VHDL/Verilog/SystemVerilog compiler
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Digital logic design tool and simulator
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