A PDF processor written in Go.

Native Operating System and Hardware Information

☔️ interface for parsing, inspecting, transforming, and serializing content through syntax trees

Intel® Performance Counter Monitor (Intel® PCM)

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Mixin is a trait/mixin and bytecode weaving framework for Java using ASM

VeeR EH1 core

Script to test single core stability, e.g. for PBO & Curve Optimizer on AMD Ryzen or overclocking/undervolting on Intel processors

A tiny Open POWER ISA softcore written in VHDL 2008

The OpenPiton Platform

RISC-V processor emulator written in Rust+WASM

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Cross-platform process cpu % and memory usage of a PID

A Forth CPU and System on a Chip, based on the J1, written in VHDL

A feature rich code block preprocessing tool.

Jest test results processor for generating a summary in HTML

A simple RISC-V processor for use in FPGA designs.