Add PLL to control clocks #607
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Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
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Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
Signed-off-by: Robert Szczepanski <[email protected]>
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This introduces PLL into HPS design with an additional option to enable/disable output clocks. It makes power consumption much higher. Initial tests with multimeter result in 70mW when CFU is disabled. It's ~30mW higher than version with DCC only presented in #597.
CI will fail because
nextpnr-nexusrequires a small fix to work. There is not needed tile generated into output.fasm. If you want to test it locally, build it as usual,prjoxidewill fail to generate a bitstream with an error:thread 'main' panicked at 'No enum named PLL_LLC.MODE in tilegroup R28C1_PLL_LLC.Then go to generated
.fasmand just search forPLL_LLC.MODEand remove a line that contains it. Run againprjoxideand it should generate a bitstream just fine: