Connect PLL's clock enable to dynamic clock control logic

Signed-off-by: Robert Szczepanski <[email protected]>

soc/hps_proto2_platform.py

@@ -7,9 +7,9 @@
 from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
 from litex.build.lattice import LatticePlatform, oxide
 from litex.build.lattice.programmer import LatticeProgrammer
-from litex.soc.cores.clock import NXOSCA, NXPLL
+from litex.soc.cores.clock import NXOSCA
 # from litex.soc.cores.ram import NXLRAM
-from hps_lattice_nx import NXLRAM
+from hps_lattice_nx import NXLRAM, NXPLL
 
 hps_io = [
     ("done", 0, Pins("A5"), IOStandard("LVCMOS18H")),
@@ -100,6 +100,12 @@ def __init__(self, platform, sys_clk_freq):
             AsyncResetSynchronizer(self.cd_cfu, ~self.sys_pll.locked | (por_counter != 0)),
         ]
 
+    def do_finalize(self):
+        self.comb += [
+            self.sys_pll.enable.sys.eq(self.sys_clk_enable),
+            self.sys_pll.enable.cfu.eq(self.cfu_clk_enable),
+        ]
+
 
 _nextpnr_report_filename = 'nextpnr-nexus-report.json'