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Pull requests: efabless/caravel_mgmt_soc_litex

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Pull requests list

Bug fixes: verilog/dv/tests-standalone/uart
#138 opened Sep 8, 2024 by edowson Loading…
Fix bug at user APIs access type
#137 opened Apr 15, 2024 by M0stafaRady Loading…
Remove in correct double declaration of reg_debug_2 and reg_debug_1 defs.h
#134 opened Dec 4, 2023 by M0stafaRady Loading…
1
Added an initialization loop to the SPI flash emulation module
#133 opened Nov 15, 2023 by RTimothyEdwards Loading…
@RTimothyEdwards
1
Create release CI
#123 opened Feb 28, 2023 by marwaneltoukhy Loading…
Update Litex mgmt soc
#122 opened Feb 3, 2023 by tmichalak Loading…
5
Remove verilog/rtl/RAM128.v
#118 opened Nov 25, 2022 by antonblanchard Loading…
2nd attempt to push the simulation of caravan I/O and the simulation Verilog testbenches and simulation
#104 opened Oct 20, 2022 by RTimothyEdwards Loading…
@RTimothyEdwards
In verilog model of standard cells, fix "notifier" register definition flow Changes to Makefile and process flow invalid This doesn't seem right
#39 opened Jul 8, 2022 by derekcom17 Loading…
1
fix issue_34 flow Changes to Makefile and process flow
#35 opened Apr 4, 2022 by suppamax Loading…
Wishbone test duplicate This issue or pull request already exists invalid This doesn't seem right
#33 opened Mar 23, 2022 by suppamax Loading…
3
extended irq test flow Changes to Makefile and process flow simulation Verilog testbenches and simulation
#31 opened Mar 21, 2022 by suppamax Loading…
verilog/dv/make: fix typo in comments flow Changes to Makefile and process flow
#28 opened Mar 17, 2022 by proppy Loading…
Fix DFFRAM when building non gate level tests error Something isn't working RTL Changes to verilog source
#18 opened Feb 18, 2022 by antonblanchard Loading…
1
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