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Most issues
Fewest issues
deferred
deferred
Deferred until next development cycle
documentation
documentation
Improvements or additions to documentation
4
duplicate
duplicate
This issue or pull request already exists
1
ECO
ECO
Engineering change order (post-PnR)
enhancement
enhancement
New feature or request
2
error
error
Something isn't working
9
flow
flow
Changes to Makefile and process flow
8
good first issue
good first issue
Good for newcomers
help wanted
help wanted
Extra attention is needed
invalid
invalid
This doesn't seem right
3
PnR
PnR
Changes to Place & Route files
1
question
question
Further information is requested
1
RTL
RTL
Changes to verilog source
4
SDC
SDC
Timing files
1
simulation
simulation
Verilog testbenches and simulation
4
wontfix
wontfix
This will not be worked on
1