How to connect the test to my SV design file, and How do I get the feedback that the test has passed or failed?

[AhmedAmrAbdellatif1]

Hello everyone,

I've designed an RISCV architecture and i want to test it using RISCV-DV.
So, is there anyone can guide me what should i exactly do to test my .sv design files and how to get the feedback of the passing or failing?

Thanks in advance.

[MikeOpenHWGroup]

Hi @AhmedAmrAbdellatif1. I think what you are asking about is outside the scope of riscv-dv. There are several open-source implementations of verification environments that you could look at:

• This presentation by the original developers of riscv-dv provides an overview of how riscv-dv can be used to create a self-checking testbench environment. (I do not know if an example implementation of that testbench is available.)
• The Ibex core, managed by lowRISC has an excellent SV/UVM environment.
• CORE-V-VERIF is the OpenHW Group's SV/UVM environment for multiple cores (including one that is a fork of Ibex).
• Wally is another OpenHW project that uses a different SV environment.

And of course there are many commercial products available as well (some of which integrate riscv-dv!).

The goals of each of these are slightly different from one another, so you'll want to consider your needs and the goals of your project before deciding on a path forward.