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AhmedAmrAbdellatif1/README.md

Hi 👋, I'm Ahmed Amr Abdellatif

Passionate About FPGA and ASIC Design & Digital Verification

Processor

ahmedamrabdellatif1

  • 💬 Ask me about Digital Design and Verification

  • 📫 How to reach me [email protected]

  • 📄 Know about my experiences from my CV

Connect with me:

ahmed-amr-abdellatif jubaskii

ahmedamrabdellatif1

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  1. Multi-Clock-Domain-System Multi-Clock-Domain-System Public

    Design & Implementation of Multi Clock Domain System using Verilog HDL

    Verilog 6