Patch 1.0 RTL with Lint Fixes

.github/workflows/build-test-verilator.yml

@@ -11,7 +11,7 @@ on:
 
 env:
   CARGO_INCREMENTAL: 0
-  SCCACHE_VERSION: 0.3.3
+  SCCACHE_VERSION: 0.8.1
   RISCV_VERSION: v12.1.0
   VERILATOR_VERSION: v5.012
   PKG_CONFIG_PATH: /opt/verilator/share/pkgconfig

.github/workflows/interactive-debugging.yml

@@ -16,8 +16,7 @@ jobs:
 
     env:
       CARGO_INCREMENTAL: 0
-      SCCACHE_VERSION: 0.3.3
-      # TODO: To update to 5.006, clean up lint errors
+      SCCACHE_VERSION: 0.8.1
       VERILATOR_VERSION: v5.012
       SCCACHE_GHA_CACHE_TO: sccache-verilator-10000
       SCCACHE_GHA_CACHE_FROM: sccache-verilator-
@@ -94,7 +93,7 @@ jobs:
 
     env:
       CARGO_INCREMENTAL: 0
-      SCCACHE_VERSION: 0.3.3
+      SCCACHE_VERSION: 0.8.1
       # A custom fork is needed to allow bypassing core examination and accessing
       # peripherals regardless of core state.
       OPENOCD_REPO: https://github.com/antmicro/openocd

README.md

@@ -14,7 +14,7 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Caliptra Hands-On Guide** #
-_*Last Update: 2024/01/17*_
+_*Last Update: 2024/05/17*_
 
 
 ## **Tools Used** ##
@@ -51,6 +51,16 @@ GCC:
  - G++ Used to compile Verilator objects and test firmware
    - `g++ (GCC) 11.2.0`
 
+RDL Compiler:
+ - systemrdl-compiler==1.27.3
+ - peakrdl-systemrdl==0.3.0
+ - peakrdl-regblock==0.21.0
+ - peakrdl-uvm==2.3.0
+ - peakrdl-ipxact==3.4.3
+ - peakrdl-html==2.10.1
+ - peakrdl-cheader==1.0.0
+ - peakrdl==1.1.0
+
 Other:
  - Playbook (Microsoft Internal workflow management tool)
 

Release_Notes.md

@@ -14,11 +14,46 @@ See the License for the specific language governing permissions and<BR>
 limitations under the License.*_<BR>
 
 # **Release Notes** #
-_*Last Update: 2024/01/18*_
+_*Last Update: 2024/06/28*_
 
-## Rev 1p0 ##
+### Rev 1p0p2 ###
 
-### Rev 1p0 release date: 2024/01/18 ###
+#### Rev 1p0p2 release date: 2024/06/28 ####
+  - Modifications for clean Lint
+    * Replace casez with case
+    * Replace 2-state with 4-state typedefs, parameters, enums
+    * Replace 'reg' with 'logic' type
+    * Radix fixes for many signals
+    * Logical/boolean operator fixes
+    * Logic reorganization to resolve undriven ICache signals in RV core
+    * Fixes for redundant logic in RV core
+    * Logically equivalent code adjustments to resolve potential index-out-of-bounds errors
+    * Declare synthesizable package functions as automatic
+    * Declare names for unnamed generate blocks
+  - Update PeakRDL tool version and regenerate reg files to resolve lint issues
+  - Update HW\_REV\_ID bit-map and configure value to 1.0.2
+
+#### Bug Fixes ####
+[ENTROPY\_SRC] Entropy source sfifo signal unable to exit reset #503 #506
+[PV] Async reset condition missing for `nonce_offset_i` #339 #444 #483
+[KV] Resolve a potential vulnerability in Key Vault usage #528
+[JTAG] VeeR JTAG access only with debug unlocked; Caliptra JTAG access with debug unlocked or manufacturing #528
+[JTAG] Enable JTAG interface to be used while boot FSM is halted at breakpoint #541
+
+## Previous Releases ##
+
+### Rev 1p0p1 ###
+
+#### Rev 1p0p1 release date: 2024/02/20 ####
+  - NOTE: v1.0.1 patch version was committed to the patch_v1.0 branch,
+    but no tag was created on GitHub and the HW_REV_ID field was not updated.
+
+#### Bug Fixes ####
+[RTL] Add connection for JTAG TDO enable signal #415 #425
+
+### Rev 1p0 ###
+
+#### Rev 1p0 release date: 2024/01/18 ####
 - Caliptra Hardware Specification: Markdown conversion
 - Caliptra Integration specification update with synthesis warnings and jtag tck requirement
 - Caliptra README updates to clarify test cases and running with VCS
@@ -33,11 +68,9 @@ _*Last Update: 2024/01/18*_
   - Remove TODO comments on caliptra_top ports
   - Remove JTAG IDCODE command from RISC-V processor
 
-### Bug Fixes ###
+#### Bug Fixes ####
 [MBOX] Fix ICCM Uncorrectable ECC error driving hw_error_non_fatal bit for LSU reads
 
-## Previous Releases ##
-
 ### Rev 1p0-rc1 ###
 
 #### Rev 1p0-rc1 release date: 2023/11/03 (1p0 version pending ROM release for official declaration) ###

src/aes/config/compile.yml

@@ -39,3 +39,7 @@ targets:
       - $COMPILE_ROOT/rtl/aes_prng_masking.sv
       - $COMPILE_ROOT/rtl/aes_key_expand.sv
     tops: [aes_cipher_core]
+  rtl_lint:
+    directories: []
+    waiver_files: []
+    tops: [aes_cipher_core]

src/aes/rtl/aes_pkg.sv

@@ -68,7 +68,7 @@ parameter masking_lfsr_perm_t RndCnstMaskingLfsrPermDefault = {
   256'h808d419d63982a16995e0e3b57826a36718a9329452492533d83115a75316e15
 };
 
-typedef enum integer {
+typedef enum logic [31:0] {
   SBoxImplLut,                   // Unmasked LUT-based S-Box
   SBoxImplCanright,              // Unmasked Canright S-Box, see aes_sbox_canright.sv
   SBoxImplCanrightMasked,        // First-order masked Canright S-Box

src/aes/rtl/aes_reg_pkg.sv

@@ -336,7 +336,7 @@ package aes_reg_pkg;
   parameter logic [0:0] AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL = 1'h 0;
 
   // Register index
-  typedef enum int {
+  typedef enum logic [31:0] {
     AES_ALERT_TEST,
     AES_KEY_SHARE0_0,
     AES_KEY_SHARE0_1,

src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv

@@ -132,7 +132,7 @@ module caliptra_prim_packer_fifo #(
 
     assign lsb_is_one = {{DepthW{1'b0}},1'b1};
     assign max_value = FullDepth;
-    assign rdata_shifted = data_q >> ptr_q*OutW;
+    assign rdata_shifted = MaxW'(data_q >> ptr_q*OutW);
     assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
     assign clear_data = (ClearOnRead && clear_status) || clr_q;
     assign load_data = wvalid_i && wready_o;

src/caliptra_prim/rtl/caliptra_prim_pkg.sv

@@ -9,7 +9,7 @@
 package caliptra_prim_pkg;
 
   // Implementation target specialization
-  typedef enum integer {
+  typedef enum logic [31:0] {
     ImplGeneric,
     ImplXilinx,
     ImplBadbit

src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv

@@ -25,17 +25,19 @@ package caliptra_prim_util_pkg;
    *   vector value. The argument shall be treated as an unsigned
    *   value, and an argument value of 0 shall produce a result of 0.
    */
-  function automatic integer _clog2(integer value);
-    integer result;
-    // Use an intermediate value to avoid assigning to an input port, which produces a warning in
-    // Synopsys DC.
-    integer v = value;
-    v = v - 1;
-    for (result = 0; v > 0; result++) begin
-      v = v >> 1;
-    end
-    return result;
-  endfunction
+
+  //Function causing LINT errors. Not used in current codebase
+  //deprecated and replaced by $clog2() //function automatic integer _clog2(integer value);
+  //deprecated and replaced by $clog2() //  integer result;
+  //deprecated and replaced by $clog2() // Use an intermediate value to avoid assigning to an input port, which produces a warning in
+  //deprecated and replaced by $clog2() // Synopsys DC.
+  //deprecated and replaced by $clog2() //  integer v = value;
+  //deprecated and replaced by $clog2() //  v = v - 1;
+  //deprecated and replaced by $clog2() //  for (result = 0; v > 0; result++) begin
+  //deprecated and replaced by $clog2() //    v = v >> 1;
+  //deprecated and replaced by $clog2() //  end
+  //deprecated and replaced by $clog2() //  return result;
+  //deprecated and replaced by $clog2() //endfunction
 
 
   /**

src/csrng/config/compile.yml

@@ -41,6 +41,11 @@ targets:
       - $COMPILE_ROOT/rtl/csrng_cmd_stage.sv
       - $COMPILE_ROOT/rtl/csrng.sv
     tops: [csrng]
+  rtl_lint:
+    directories: []
+    waiver_files:
+      - $MSFT_REPO_ROOT/src/csrng/config/design_lint/sglint_waivers
+    tops: [csrng]
 ---
 provides: [csrng_tb]
 schema_version: 2.4.0

src/csrng/rtl/csrng.sv

@@ -15,7 +15,7 @@ module csrng
 #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplCanright,
   parameter logic [csrng_reg_pkg::NumAlerts-1:0] AlertAsyncOn = {csrng_reg_pkg::NumAlerts{1'b1}},
-  parameter int NHwApps = 2,
+  parameter logic [31:0] NHwApps = 2,
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0),
   parameter AHBDataWidth = 64,

src/csrng/rtl/csrng_block_encrypt.sv

@@ -7,10 +7,10 @@
 
 module csrng_block_encrypt import csrng_pkg::*; #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
-  parameter int Cmd = 3,
-  parameter int StateId = 4,
-  parameter int BlkLen = 128,
-  parameter int KeyLen = 256
+  parameter logic [31:0] Cmd = 3,
+  parameter logic [31:0] StateId = 4,
+  parameter logic [31:0] BlkLen = 128,
+  parameter logic [31:0] KeyLen = 256
 ) (
   input logic                clk_i,
   input logic                rst_ni,
@@ -33,9 +33,9 @@ module csrng_block_encrypt import csrng_pkg::*; #(
   output logic [2:0]         block_encrypt_sfifo_blkenc_err_o
 );
 
-  localparam int BlkEncFifoDepth = 1;
-  localparam int BlkEncFifoWidth = StateId+Cmd;
-  localparam int NumShares = 1;
+  localparam logic[31:0] BlkEncFifoDepth = 1;
+  localparam logic[31:0] BlkEncFifoWidth = StateId+Cmd;
+  localparam logic[31:0] NumShares = 1;
 
   // signals
   // blk_encrypt_in fifo

src/csrng/rtl/csrng_cmd_stage.sv

@@ -6,9 +6,9 @@
 //
 
 module csrng_cmd_stage import csrng_pkg::*; #(
-  parameter int CmdFifoWidth = 32,
-  parameter int CmdFifoDepth = 16,
-  parameter int StateId = 4
+  parameter logic [31:0] CmdFifoWidth = 32,
+  parameter logic [31:0] CmdFifoDepth = 16,
+  parameter logic [31:0] StateId = 4
 ) (
   input logic                        clk_i,
   input logic                        rst_ni,
@@ -48,9 +48,9 @@ module csrng_cmd_stage import csrng_pkg::*; #(
 );
 
   // Genbits parameters.
-  localparam int GenBitsFifoWidth = 1+128;
-  localparam int GenBitsFifoDepth = 1;
-  localparam int GenBitsCntrWidth = 13;
+  localparam logic[31:0] GenBitsFifoWidth = 1+128;
+  localparam logic[31:0] GenBitsFifoDepth = 1;
+  localparam logic[31:0] GenBitsCntrWidth = 13;
 
   // Command FIFO.
   logic [CmdFifoWidth-1:0] sfifo_cmd_rdata;
@@ -191,7 +191,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
     .set_cnt_i(sfifo_cmd_rdata[24:12]),
     .incr_en_i(1'b0),
     .decr_en_i(cmd_gen_cnt_dec), // Count down.
-    .step_i(GenBitsCntrWidth'(1)),
+    .step_i(GenBitsCntrWidth'(unsigned'(1))),
     .cnt_o(cmd_gen_cnt),
     .cnt_next_o(),
     .err_o(cmd_gen_cnt_err_o)
@@ -224,7 +224,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   // Minimum Hamming weight: 1
   // Maximum Hamming weight: 7
   //
-  localparam int StateWidth = 8;
+  localparam logic[31:0] StateWidth = 8;
   typedef    enum logic [StateWidth-1:0] {
     Idle      = 8'b00011011, // idle
     ArbGnt    = 8'b11110101, // general arbiter request
@@ -285,7 +285,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
           cmd_gen_1st_req = 1'b1;
           cmd_arb_sop_o = 1'b1;
           cmd_fifo_pop = 1'b1;
-          if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(1)) begin
+          if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(unsigned'(1))) begin
             cmd_gen_cnt_last = 1'b1;
           end
           if (cmd_len == '0) begin
@@ -350,7 +350,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
           cmd_gen_inc_req = 1'b1;
           state_d = GenCmdChk;
           // Check for final genbits beat.
-          if (cmd_gen_cnt == GenBitsCntrWidth'(1)) begin
+          if (cmd_gen_cnt == GenBitsCntrWidth'(unsigned'(1))) begin
             cmd_gen_cnt_last = 1'b1;
           end
         end

src/csrng/rtl/csrng_core.sv

@@ -13,7 +13,7 @@ module csrng_core
  import lc_ctrl_pkg::*;
 #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
-  parameter int NHwApps = 2,
+  parameter logic [31:0] NHwApps = 2,
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0)
 ) (
@@ -60,26 +60,26 @@ module csrng_core
   import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
   import caliptra_prim_mubi_pkg::mubi4_test_invalid;
 
-  localparam int NApps = NHwApps + 1;
-  localparam int AppCmdWidth = 32;
-  localparam int AppCmdFifoDepth = 2;
-  localparam int GenBitsWidth = 128;
-  localparam int Cmd = 3;
-  localparam int StateId = 4;
-  localparam int KeyLen = 256;
-  localparam int BlkLen = 128;
-  localparam int SeedLen = 384;
-  localparam int CtrLen = 32;
-  localparam int NBlkEncArbReqs = 2;
-  localparam int BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd;
-  localparam int NUpdateArbReqs = 2;
-  localparam int UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd;
-  localparam int MaxClen = 12;
-  localparam int ADataDepthWidth = SeedLen/AppCmdWidth;
-  localparam unsigned ADataDepthClog = $clog2(ADataDepthWidth)+1;
-  localparam int CsEnableCopies = 53;
-  localparam int LcHwDebugCopies = 1;
-  localparam int Flag0Copies = 3;
+  localparam logic [31:0] NApps = NHwApps + 1;
+  localparam logic [31:0] AppCmdWidth = 32;
+  localparam logic [31:0] AppCmdFifoDepth = 2;
+  localparam logic [31:0] GenBitsWidth = 128;
+  localparam logic [31:0] Cmd = 3;
+  localparam logic [31:0] StateId = 4;
+  localparam logic [31:0] KeyLen = 256;
+  localparam logic [31:0] BlkLen = 128;
+  localparam logic [31:0] SeedLen = 384;
+  localparam logic [31:0] CtrLen = 32;
+  localparam logic [31:0] NBlkEncArbReqs = 2;
+  localparam logic [31:0] BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd;
+  localparam logic [31:0] NUpdateArbReqs = 2;
+  localparam logic [31:0] UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd;
+  localparam logic [31:0] MaxClen = 12;
+  localparam logic [31:0] ADataDepthWidth = SeedLen/AppCmdWidth;
+  localparam logic [31:0] ADataDepthClog = $clog2(ADataDepthWidth)+1;
+  localparam logic [31:0] CsEnableCopies = 53;
+  localparam logic [31:0] LcHwDebugCopies = 1;
+  localparam logic [31:0] Flag0Copies = 3;
 
   // signals
   // interrupt signals