modify riscv-dv

chipsalliance · Jul 8, 2024 · cb6122d · cb6122d
1 parent 12032d7
commit cb6122d
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/.github/workflows/test-riscv-dv.yml b/.github/workflows/test-riscv-dv.yml
@@ -342,6 +342,12 @@ jobs:
 
           ${RISCV_GCC} --version
 
+          # Enable U mode only in simulators.
+          # Change the command line of spike to execute with '--priv=mu'. The default is 'msu'.
+          sed -i '/spike/s/--isa=<variant> /--isa=<variant> --priv=mu /g' third_party/riscv-dv/yaml/iss.yaml
+          # Change the command line of whisper to execute with '--isa <variant>u'.
+          sed -i '/whisper/s/--isa <variant>/--isa <variant>u/g' third_party/riscv-dv/yaml/iss.yaml
+
           pushd tools/riscv-dv
             make -j`nproc` \
               RISCV_DV_TEST=${{ matrix.test }} \