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vivado

Here are 523 public repositories matching this topic...

hls4ml

fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS

python machine-learning fpga neural-network hls keras pytorch vivado vivado-hls onnx intel-hls

Updated Jul 9, 2024
C++

hdl-modules

hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Updated Jul 9, 2024
VHDL

tsfpga

tsfpga / tsfpga

A flexible and scalable development platform for modern FPGA projects.

asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit

Updated Jul 9, 2024
Python

PyFPGA / pyfpga

A Python package to use FPGA development tools programmatically.

Updated Jul 8, 2024
Python

prjxray

f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.

toolchain tools fpga xilinx vivado fuzzer xilinx-fpga bitstream artix7 artix kintex7 symbiflow

Updated Jul 6, 2024
Python

Tosainu / docker-vivado

Dockerfile for AMD/Xilinx Vivado

dockerfile fpga xilinx vivado

Updated Jul 6, 2024
Dockerfile

htmos6 / Flex-PWM500

The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.

vhdl vivado testbench xsim vhdl-testbench

Updated Jul 4, 2024
VHDL

Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Jul 5, 2024
Java

htmos6 / Swiss-Stopwatch

Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.

vhdl vivado xsim

Updated Jul 3, 2024
VHDL

rishz09 / digital-safe-verilog

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

verilog vivado digital-design verilog-project pynq-z2 vivado-simulator digital-safe

Updated Jul 1, 2024
Tcl

Tosainu / ultra96-fractal

Hardware accelerated Julia set explorer running on Ultra96

fpga zynq xilinx vivado systemverilog petalinux julia-sets ultra96

Updated Jun 30, 2024
C++

iDoka / eda-scripts

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

gitignore asic fpga gitattributes eda versioning xilinx vivado pll ucf design-automation xdc mmcm

Updated Jun 30, 2024
Shell

KOTerra / Digital-VHDL-Locker

A digital locker made for Nexys A7 using Xilinx Vivado and VHSIC Hardware Description Language

vhdl vivado nexys-a7

Updated Jun 28, 2024
VHDL

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Jul 8, 2024
Python

MJoergen / HyperRAM

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Jul 8, 2024
VHDL

thuvasooriya / vivado4mac

tryin to run vivado on mac

macos docker mac vivado xquartz apple-silicon

Updated Jun 26, 2024
C

Indithem / COL215-hardware-3

Filters and displays an image loaded into ROM through a VGA

vivado vga xilinx-vivado col215

Updated Jun 26, 2024
VHDL

amirah-sri / all_verilog

I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

Updated Jun 26, 2024
Verilog

mshr-h / vscode-verilog-hdl-support

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Jul 9, 2024
TypeScript

multigcs / FPGA-blinky

template fpga makefile diamond vivado blinky yosys gowin nextpnr ise-webpack

Updated Jun 24, 2024
Makefile

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