An abstraction library for interfacing EDA tools
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Updated
Jun 28, 2024 - Python
An abstraction library for interfacing EDA tools
HDL support for VS Code
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
XCrypto: a cryptographic ISE for RISC-V
SHA256 in (System-) Verilog / Open Source FPGA Miner
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
Quickstart guide on Icarus Verilog.
💎 A 32-bit ARM Processor Implementation in Verilog HDL
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
mirror of https://git.elphel.com/Elphel/vdt-plugin
Example of Python and PyTest powered workflow for a HDL simulation
Example of how to get started with olofk/fusesoc.
👶🏻 My first baby steps into the world of NoC
🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
Apache 2.0 licensed copy of the Xilinx Unisim library.
iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
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