processor-design
Here are 59 public repositories matching this topic...
CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations
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Nov 28, 2023 - Python
Multi-core Processor Design for Matrix Multiplication Using Verilog
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Dec 20, 2021 - Verilog
Designed the revised single-cycle datapath and revised control units which make a processor that executes the instructions as well as the instructions implemented already in the design.
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Jun 7, 2022 - Verilog
A 2-stage pipeline processor implemented in C++.
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May 30, 2022 - C++
Verilog Implementation of a Z80 Compatible Processor Architecture - Lab Report
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Mar 28, 2021 - TeX
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
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Aug 30, 2023 - JavaScript
Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)
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Mar 10, 2023 - SystemVerilog
Computer Architecture Project Description
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Nov 17, 2023 - TeX
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Dec 10, 2018 - VHDL
Projeto de leitura e processamento de dados de CSV em Node.js.
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May 5, 2024 - JavaScript
Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis
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Oct 1, 2023 - Assembly
Implementing a 32-bit processor using RISC-V architecture.
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Dec 23, 2023 - SystemVerilog
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Feb 2, 2021 - Verilog
A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.
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Jun 22, 2022 - HTML
This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.
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Dec 29, 2023 - SystemVerilog
Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture
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Dec 30, 2023 - SystemVerilog
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
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Jul 4, 2024 - C
18-bit processor implementation using Logisim
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Jul 10, 2023 - Python
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA
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Aug 6, 2023 - Verilog
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