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Synthesizable Single-Cycle RISCV-RV32I (tested on DE2)

The milestone for the CA class: Implementing RV32I on DE2. Thank you my teammate for supporting me throughout this project.

Note

  • Don't read the code before thoroughly understanding the spec.
  • Please explore the report, doc, rtl, tb folders on your own.
  • A higher version will be updated once I complete it.

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Single-Cycle RISCV-RV32I on FPGA

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