Pinned Loading

1. SHA3_hw SHA3_hw Public

   Hardware implementation of the SHA-3, published in FIPS 202 by NIST.

   SystemVerilog

2. fir_filter fir_filter Public

   Hardware implementation of FIR filter (DSP)

   HTML

3. pipeline_notusingsram pipeline_notusingsram Public

   Pipeline 5 stage RISCV-RV32I (tested on DE2)

   SystemVerilog

4. template template Public

   Latex Template

   TeX

5. mini_lecture mini_lecture Public

   Some topics that I done to improve my RTL skill

   Verilog

6. singcyle_notusingsram singcyle_notusingsram Public

   Single-Cycle RISCV-RV32I on FPGA

   SystemVerilog