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CORE_V_MCU high level design specs #550

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CORE_V_MCU high level design specs

CORE_V_MCU high level design specs #550

Re-run triggered January 18, 2024 18:51
@DBeesDBees
#328
cst-rameez:rameezs/core_v_mcu_hls
Status Success
Total duration 51s
Artifacts –

lint.yml

on: pull_request
Format Verilog Sources
40s
Format Verilog Sources
Vendor Up-to-Date
41s
Vendor Up-to-Date
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