This release serves as a snapshot for the April 15th deadline for the EECE4632 FPGA Hardware Software Codesign course. This revision contains:
- Updated TCL files including BRAM updating from the processor for easy tuning
- AP Fixed point representation of filter coefficients in HLS
- MATLAB script for signal processing tuning
NOTE: This iteration shows the ability to tune the filter over an AXI BRAM controller connected to the PS. It also adds in fixed point arithmetic, if the fixedpoint bitstream is loaded. The interfaces between the BRAM bitstream and the fixedpoint bitstream should be the same