April 15th Deadline

This release serves as a snapshot for the April 15th deadline for the EECE4632 FPGA Hardware Software Codesign course. This revision contains:

• Updated TCL files including BRAM updating from the processor for easy tuning
• AP Fixed point representation of filter coefficients in HLS
• MATLAB script for signal processing tuning

NOTE: This iteration shows the ability to tune the filter over an AXI BRAM controller connected to the PS. It also adds in fixed point arithmetic, if the fixedpoint bitstream is loaded. The interfaces between the BRAM bitstream and the fixedpoint bitstream should be the same

March 28th Deadline

This release serves as a snapshot for the March 28th deadline for the EECE4632 FPGA Hardware Software Codesign course. This revision contains:

• HLS implementation of Biquad Filter
• Vivado Project (TCL files) for implementing HLS IP
• Jupyter Notebooks with results of testing

NOTE: This iteration shows progress in that the Python is able to communicate to the HLS block via AXI Stream, and that the coefficients of the filter are changing the data put through. To showcase this, a filter with random coefficients was made and a filter with zeroed coefficients, which produced vastly different outputs.

February 29th Deadline

This release serves as a snapshot for the Februrary 29th deadline for the EECE4632 FPGA Hardware Software Codesign course. This revision contains:

• Initial Python implementation of a digital biquad filter
• Plotting of signal and amplitude of original and filtered signal
• Ability to tune multiple wav files around multiple center frequencies by tuning main.py
• Two unique wav files to operate and test on