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'nets argument to convert must be a signal' when working with records and functions
#1094
opened Dec 10, 2024 by
Schottkyc137
Feature request: Warning suppression and escalation to error command-line flags
wishlist
#1004
opened Sep 30, 2024 by
soronpo
Verilog - Support
celldefine
, endcelldefine
, ifdef
and else
verilog
#811
opened Dec 5, 2023 by
Blebowski
VHPI: Preserve original name case for CaseNameP and FullCaseNameP
vhpi
#723
opened Jun 18, 2023 by
Forty-Bot
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