[SeqToSV] Do not use always_ff for compreg with initializer
#7838
+44
−4
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fzi-hielscher
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Verilog/SystemVerilog
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By default SeqToSV uses
always_ffprocesses to lowerseq.compregops. This prohibits any other assignments to the register/variable in another process. Apparently, some simulators consider an initializer at the declaration to be a process. Other simulators don't, and it is also not how I would interpret the SV spec, but what do I know?I think dodging a simulator error is more important than having the
always_ff. So, this PR changes the lowering to usealwaysinstead ofalways_ffin the presence of an initializer, even if thelower-to-always-ffflag is set.See also #1310, #2110.