v0.3.0

What's Changed

• Module hierarchy tracing fixes by @mkorbel1 in #85
• Provide the ability to reserve instance names and provide + reserve definition names by @mkorbel1 in #86
• Fix typo in README by @eric-norige in #87
• Enhanced bin() to ignore '_'. Ticket - https://github.com/intel/rohd/… by @shubskmr in #88
• Add explicit width to Const generated SystemVerilog by @mkorbel1 in #94
• Refactor to combine LogicValue and LogicValues into LogicValue, plus some related adjustments by @mkorbel1 in #115
• Various features and testing for Logic and LogicValue by @mkorbel1 in #121

New Contributors

• @shubskmr made their first contribution in #88

Full Changelog: v0.2.0...v0.3.0