v0.5.3

What's Changed

• Absolute value by @dmetis in #442
• Make conditional assign a little more optimistic with invalid values by @mkorbel1 in #459
• Add youtube channel link to Readme.md by @quekyj in #460
• ROHD Module Hierarchy and Signals Visualization (Flutter UI) by @quekyj in #435
• Update analysis options and doc checks for Dart 3.3.0 by @mkorbel1 in #463
• Fix documentation generation by @mkorbel1 in #467
• Simulator upgrades for rohme compatibility (registering now and cancelling) by @AdamRose66 in #468
• Issue #377: assign a logic subset to logic (array) by @RPG-coder-intc in #456
• Fix a bug where array port element naming collisions with port names caused misconnections by @mkorbel1 in #473
• chore(devtool): build devtool artifact and commit to other branch by @quekyj in #461
• fix: update flutter version to the latest by @quekyj in #474
• Refactored tick() in simulator.dart by @AdamRose66 in #475
• Update to use new runners in github actions by @mkorbel1 in #417
• Adjust CI timeout and runners by @mkorbel1 in #480

New Contributors

• @AdamRose66 made their first contribution in #468

Full Changelog: v0.5.2...v0.5.3

v0.5.2

What's Changed

• Allow constant Z driving to show up in SV without error by @mkorbel1 in #441
• Logic value test improvement and minor fixes by @mjayasim9 in #422
• Optimize performance of Combinational.ssa driver search by @mkorbel1 in #443
• Support compiling ROHD to JavaScript by @mkorbel1 in #445
• Get a Logic of a Logic List via an index by @RPG-coder-intc in #438
• Pipeline fixes and improvements by @mkorbel1 in #447
• Update counter example to be simpler and a better reference by @mkorbel1 in #448
• Update default permissions in GH actions by @mkorbel1 in #452
• Update some pages of the user guide by @mkorbel1 in #453
• Fix defaultNextState diagram generation in FSM by @mkorbel1 in #454
• Make Simulator.endSimulation return a Future by @mkorbel1 in #455
• Fix bugs in LogicStructure instrumentation calls to packed and changed issues across Simulator.reset by @mkorbel1 in #458

Full Changelog: v0.5.1...v0.5.2

v0.5.1

What's Changed

• Sort ports and internal signals, fix #395 by @mkorbel1 in #420
• Allow multiple nonblocking assignments, fix #321 by @mkorbel1 in #421
• Fix bug where generated SV has lint issues with plus and shift-left due to SV width expansion by @mkorbel1 in #423
• Signal naming improvements by @mkorbel1 in #439
• More module and signal naming improvements by @mkorbel1 in #440

Full Changelog: v0.5.0...v0.5.1

v0.5.0

What's Changed

• Edit some project files by @chykon in #262
• Fix doc check by @mkorbel1 in #263
• Update contribution style section by @mkorbel1 in #269
• Fixes: 223 and Fixes: 224 by @akshay-wankhede in #247
• Chapter 1 - bootcamp (Introduction to ROHD) by @quekyj in #266
• Add check for Markdown links in CI by @chykon in #276
• Add recommended extensions for VSCode by @chykon in #277
• Add markdownlint extension by @chykon in #279
• Format Markdown files by @chykon in #282
• Add Markdown linting to CI by @chykon in #280
• Chapter 2 bootcamp tutorials by @quekyj in #278
• Slightly fix the example files by @chykon in #267
• Create a unified timestamp format by @chykon in #265
• 250 fsm state diagram mermaid generator by @quekyj in #251
• Small set of CI/CD configuration changes by @chykon in #297
• Chapter 3 bootcamp by @quekyj in #288
• Added no print to the register time by @quekyj in #301
• First implementation for don't care scenarios by @dmetis in #294
• Fix #295, signed arithmetic shift right by @mkorbel1 in #296
• Fix long comment lines not caught by lint by @mkorbel1 in #306
• [Fix 324] Add WaveDumper ability to create missing output directories by @chykon in #326
• Update chapter 3 bootcamp by @quekyj in #333
• Minor improvements to benchmark files by @chykon in #325
• Small improvements for Architecture.md, TreeExample.md by @chykon in #327
• update chapter 2 bootcamp by @quekyj in #310
• Chapter 4 bootcamp by @quekyj in #339
• Small improvements for CONTRIBUTING.md by @chykon in #329
• [Issue-281] port initialized with empty name by @quekyj in #303
• [Issue 246] SynthBuilder should check for Module.build() by @quekyj in #340
• Combinational sensitivity refactor and SSA by @mkorbel1 in #344
• Optimize guard subscription performance in Combinational by @mkorbel1 in #346
• Optimize Sets, Maps, and Module.input/output getters by @mkorbel1 in #347
• Fix #348: make Case and CaseZ use edge-sampled signals for expression evaluation by @mkorbel1 in #349
• Issue#140: Added gt and gte for for consistency to Logic by @Sanchit-kumar in #351
• Fix #148: Implemented neq by @Sanchit-kumar in #350
• Simulation performance improvements for conditional assignments by @mkorbel1 in #352
• Website / user-guide by @quekyj in #359
• Issue #336: Added power functionality by @Sanchit-kumar in #356
• [issue#137]: Add mechanism for reset all flop of Sequential by @RPG-coder-intc in #302
• Issue#334: Added enable signal to flipflop by @Sanchit-kumar in #357
• Chapter 5 bootcamp tutorial by @quekyj in #358
• Check devcontainer in CI by @mkorbel1 in #370
• Issue#316 Prevent self connecting logic by @Sanchit-kumar in #368
• Issue:#337 Added clog2 by @Sanchit-kumar in #361
• LogicStructure and LogicArray by @mkorbel1 in #375
• 232 add a mechanism for generating random logic values by @quekyj in #362
• Chapter 6 bootcamp by @quekyj in #369
• Add PairInterface by @mkorbel1 in #379
• Issue#257: Added flop like function to construct FlipFlop by @Sanchit-kumar in #381
• Fix #382, if block exceptions when else is wrong by @mkorbel1 in #383
• Issue#371 Made LogicValue Comparable by @Sanchit-kumar in #373
• Fix bug with SSA reuse of signals by @mkorbel1 in #387
• Add previousValue to Logic by @mkorbel1 in #385
• Fix bug where FSM may cause inferred latch by @mkorbel1 in #390
• Add branch coverage to script by @mkorbel1 in #389
• Chapter 7 bootcamp by @quekyj in #380
• Fix bugs where SSA could potentially generate inferred latches by @mkorbel1 in #391
• Fix some sensitive tests to be more robust by @mkorbel1 in #397
• Refactor docs and README for website by @mkorbel1 in #388
• Fix blog link in README by @mkorbel1 in #398
• Cases by @mjayasim9 in #386
• Lint cleanup by @mkorbel1 in #402
• Add chapter 8 tutorials by @quekyj in #399
• Unique case with multiple match behavior by @dmetis in #403
• Reset for flops and try ports by @mkorbel1 in #410
• Fixes for LogicValue operation bugs related to size, sign, math, and comparison by @ganewto in #319
• Fixes and improvements related to shifts by @mkorbel1 in #412
• Cleanup some doc and comments by @mkorbel1 in #413
• Updates to FSM and Pipeline abstractions and documentation by @mkorbel1 in #414
• Chapter 9 - Tutorials on ROHD Verification Framework by @quekyj in #407
• Mark inputs as protected in Module by @mkorbel1 in #416
• Gates should output X (never Z) when inputs are invalid by @dmetis in #393

New Contributors

• @dmetis made their first contribution in #294
• @Sanchit-kumar made their first contribution in #351
• @mjayasim9 made their first contribution in #386
• @ganewto made their first contribution in #319

Full Changelog: v0.4.2...v0.5.0

v0.4.2

What's Changed

• Add GitHub Code Spaces configuration by @quekyj in #226
• [Fix-issue-141] Adding Logic functionality for incr(), decr(), mulAssign() & divAssign() operation by @RPG-coder-intc in #196
• Fixes: 204 by @akshay-wankhede in #220
• Add test for shuffling bits by @mkorbel1 in #237
• Added test for changed triggers on injection from changed by @mkorbel1 in #238
• [Issue-104] checks to prevent same conditional used multiple times by @quekyj in #227
• [Issue-225] Add Else.s() constructor to for single then execution by @quekyj in #229
• Fix combinational sensitivity excessive pessimism, fix #233 by @mkorbel1 in #240
• Move VCD parser for tests into utilities by @mkorbel1 in #241
• Fix README on accessing int/BigInt values of Logic by @mkorbel1 in #244
• Improve exceptions for Logic.put by @mkorbel1 in #243
• WaveDumper optimization by @mkorbel1 in #242
• [Issue-228] Make endIndex in getRange an optional positional argument, default to width by @quekyj in #231
• [Issue-133] simcompare calculate signaltowidth instead of manual input by @quekyj in #211
• Fix dart analysis issues surfaced in 2.19 by @mkorbel1 in #248
• Revert IndexError deprecation change to maintain backwards compatibility by @mkorbel1 in #249
• [Issue-234] Port should validate that names are sanitary by @quekyj in #245
• await registered actions in Simulator by @mkorbel1 in #252
• added the inline function for isValid and isFloating by @priya-t12 in #216
• Improve GitHub Codespaces configuration by @chykon in #256
• await Simulator.reset in test teardowns by @mkorbel1 in #255
• Added test to check sanitized names by @aherrera97intl in #258
• Upgrade VcdParser to handle more VCD files by @mkorbel1 in #260
• [issue#7] Adding isIn() for [], [], [], [] by @RPG-coder-intc in #259
• Updates to some documentation by @mkorbel1 in #261

New Contributors

• @priya-t12 made their first contribution in #216
• @aherrera97intl made their first contribution in #258

Full Changelog: v0.4.1...v0.4.2

v0.4.1

What's Changed

• resolves #153 by @akshay-wankhede in #171
• resolves issue #138 by @quekyj in #190
• Fixes: 157 by @akshay-wankhede in #203
• Fix bugs related to module naming and instantiation by @mkorbel1 in #207
• Allow constants for modulo and shift operations on Logic by @mkorbel1 in #208
• Fix typo on modulo test by @mkorbel1 in #209
• _Wires underneath Logics by @mkorbel1 in #199
• Fix bugs related to 64-bit int conversion, fix #212 by @mkorbel1 in #213
• [Issue-12] simpler constructor of simple control blocks by @quekyj in #210
• Replace awkward map+reduce chain with smart literal by @eric-norige in #214
• Optimize LogicValue operations to avoid Strings where possible by @mkorbel1 in #215
• [Issue-112] Automatically extract rohd version from pubspec to add into generated sv by @quekyj in #200
• Fix bug related to late connection signal prop with wires by @mkorbel1 in #218
• Fixed LogicValue hash and equality inconsistency by forcing construction consistency by @mkorbel1 in #217
• Fix the tree example doc by @mkorbel1 in #222
• [Issue-114] Add test to sequential driver on same signal to return Exception by @quekyj in #197

New Contributors

• @akshay-wankhede made their first contribution in #171
• @quekyj made their first contribution in #190

Full Changelog: v0.4.0...v0.4.1

v0.4.0

What's Changed

• Fix #163 - invalid generated SystemVerilog for bit slicing on expressions by @mkorbel1 in #164
• fix constant collapsing, fix #159 by @mkorbel1 in #160
• Fix Combinational sensitivity detection - Issue #158 by @mkorbel1 in #166
• Improve performance of Combinational execute by @mkorbel1 in #156
• Rework script "run_coverage" by @chykon in #173
• Use issue forms instead of old template by @chykon in #176
• Upgrade lints package, make lints more strict, and fix new lint errors by @mkorbel1 in #174
• [FIX-issue#99] Allowing negative logic index values by @RPG-coder-intc in #155
• Remove accidental dontDeleteTmpFiles for a bus test by @mkorbel1 in #178
• Improving GitHub Actions workflow and local testing by @chykon in #177
• Fix badges in readme after workflow changes by @mkorbel1 in #179
• Increase Dart SDK version by @chykon in #181
• Fix #183, parsing of unsigned large binary integers by @mkorbel1 in #184
• Update to contributor covenant v2.1 (fix #182) by @mkorbel1 in #185
• Expose synthesis results from synth builder (fix #172) by @mkorbel1 in #186
• Rename topModuleName to definitionName in ExternalSystemVerilogModule by @mkorbel1 in #187
• Clean up names for ports by @mkorbel1 in #188
• Add full SV reserved keyword list to sanitizer, fix #168 by @mkorbel1 in #189

New Contributors

• @chykon made their first contribution in #173
• @RPG-coder-intc made their first contribution in #155

Full Changelog: v0.3.2...v0.4.0

v0.3.2

What's Changed

• Finished commit for FSM by @shubskmr in #127
• Fix for issue #126 Simulator reset does not wait for simulation to complete and test to reproduce the issue by @madhuriakella in #131
• add modulo support by @chaparalas in #136
• Add Discord server information by @mkorbel1 in #143
• Added actions to execute at the end of the simulation by @mkorbel1 in #149
• Moved wave dump file writing to be async for performance by @mkorbel1 in #150

New Contributors

• @madhuriakella made their first contribution in #131
• @chaparalas made their first contribution in #136

Full Changelog: v0.3.1...v0.3.2

v0.3.1

What's Changed

• Fix #129, waveform dump bug for multi-bit values by @mkorbel1 in #130

Full Changelog: v0.3.0...v0.3.1

v0.3.0

What's Changed

• Module hierarchy tracing fixes by @mkorbel1 in #85
• Provide the ability to reserve instance names and provide + reserve definition names by @mkorbel1 in #86
• Fix typo in README by @eric-norige in #87
• Enhanced bin() to ignore '_'. Ticket - https://github.com/intel/rohd/… by @shubskmr in #88
• Add explicit width to Const generated SystemVerilog by @mkorbel1 in #94
• Refactor to combine LogicValue and LogicValues into LogicValue, plus some related adjustments by @mkorbel1 in #115
• Various features and testing for Logic and LogicValue by @mkorbel1 in #121

New Contributors

• @shubskmr made their first contribution in #88

Full Changelog: v0.2.0...v0.3.0