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feat: overridable corner for synthesis #566

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feat: overridable corner for synthesis #566

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63cf152
test slow corner for synthesis
kareefardi Oct 2, 2024
e017f5e
format
kareefardi Oct 2, 2024
c285b21
Make it optional
kareefardi Oct 2, 2024
a434596
Merge branch 'dev' into synthesis-corner
kareefardi Oct 15, 2024
e9a6d6f
Merge branch 'dev' into synthesis-corner
kareefardi Oct 21, 2024
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2 changes: 2 additions & 0 deletions openlane/config/pdk_compat.py
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Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,7 @@ def process_sta(key: str):
"max_ss_100C_1v60",
"max_ff_n40C_1v95",
]
new["SYNTH_CORNER"] = "*_ss_100C_1v60"
elif new["PDK"].startswith("gf180mcu"):
new["STA_CORNERS"] = [
"nom_tt_025C_5v00",
Expand All @@ -226,6 +227,7 @@ def process_sta(key: str):
"max_ss_125C_4v50",
"max_ff_n40C_5v50",
]
new["SYNTH_CORNER"] = "*_ss_125C_4v50"

new["DEFAULT_CORNER"] = f"nom_{default_pvt}"
new["LIB"] = lib_sta
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10 changes: 9 additions & 1 deletion openlane/steps/pyosys.py
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Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,12 @@ class PyosysStep(Step):
"Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.",
default="ALL",
),
Variable(
"SYNTH_CORNER",
Optional[str],
"IPVT corners to use during resizer optimizations. If unspecified, the value for `STA_CORNERS` from the PDK will be used.",
pdk=True,
),
]

@abstractmethod
Expand Down Expand Up @@ -271,7 +277,9 @@ def get_command(self, state_in: State) -> List[str]:
cmd = super().get_command(state_in)

blackbox_models = []
scl_lib_list = self.toolbox.filter_views(self.config, self.config["LIB"])
scl_lib_list = self.toolbox.filter_views(
self.config, self.config["LIB"], self.config.get("SYNTH_CORNER")
)
if self.power_defines and self.config["CELL_VERILOG_MODELS"] is not None:
blackbox_models.extend(
[
Expand Down
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