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Direct New feature or request
debug
tools using the CLI
✨ enhancement
#603
opened Nov 22, 2024 by
daquintero
Portable States
⛓️💥 breaking change
This issue may require a change to OpenLane's API
✨ enhancement
New feature or request
Unify This issue may require a change to OpenLane's API
✨ enhancement
New feature or request
common.Path
and pathlib.Path
⛓️💥 breaking change
Synthesis no longer works via Google Colab
🐞 bug
Something isn't working
workaround
This issue has an end-user workaround
#590
opened Oct 21, 2024 by
ajkourabi
--dockerized fails to start unless X11 optional directory/files exist for docker to mount
🐞 bug
Something isn't working
#580
opened Oct 14, 2024 by
dlmiles
SDC as single source of truth for clock info
⛓️💥 breaking change
This issue may require a change to OpenLane's API
✨ enhancement
New feature or request
openlane2 non going through --smoke-test
🐞 bug
Something isn't working
💬 waiting on op
This issue requires more information from its original creator
#569
opened Oct 5, 2024 by
ctalar
Allow both New feature or request
min
/ max
version of a macro library for a given corner
✨ enhancement
Add missing metrics to New feature or request
library.py
✨ enhancement
#567
opened Oct 3, 2024 by
kareefardi
Study correlation between timing values before and after routing
✨ enhancement
New feature or request
#561
opened Sep 24, 2024 by
donn
Explore integrating DRiLLS for ABC scripts
✨ enhancement
New feature or request
#559
opened Sep 23, 2024 by
donn
Explore OpenROAD local resynthesis
⛔️ blocked
This issue or PR is pending an issue with an underlying utility
✨ enhancement
New feature or request
#558
opened Sep 23, 2024 by
donn
Support for PDKs without TAP / ENDCAP cells
⛓️💥 breaking change
This issue may require a change to OpenLane's API
Warning in the PDK LEF files
⛔️ blocked
This issue or PR is pending an issue with an underlying utility
✨ enhancement
New feature or request
#550
opened Sep 18, 2024 by
kareefardi
Test case for hierarchical designs sta results and annotation
✨ enhancement
New feature or request
#547
opened Sep 5, 2024 by
kareefardi
Inject custom Verilog into the flow
⛓️💥 breaking change
This issue may require a change to OpenLane's API
#543
opened Sep 4, 2024 by
mole99
PL_MAX_DISPLACEMENT_{X,Y}
set atrociously high in both OpenLanes
⛓️💥 breaking change
Move This issue may require a change to OpenLane's API
✨ enhancement
New feature or request
SIGNAL_WIRE_RC_LAYERS
, CLOCK_WIRE_RC_LAYERS
to the relevant steps
⛓️💥 breaking change
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Updated in the last three days: updated:>2024-11-20.