add yosys.resynthesis

openlane/scripts/pyosys/synthesize.py

@@ -115,11 +115,13 @@ def openlane_synth(d, top, flatten, report_dir, *, booth=False, abc_dff=False):
 @click.option("--config-in", type=click.Path(exists=True), required=True)
 @click.option("--extra-in", type=click.Path(exists=True), required=True)
 @click.option("--lighter-dff-map", type=click.Path(exists=True), required=False)
+@click.argument("inputs", nargs=-1)
 def synthesize(
     output,
     config_in,
     extra_in,
     lighter_dff_map,
+    inputs,
 ):
     config = json.load(open(config_in))
     extra = json.load(open(extra_in))
@@ -154,7 +156,17 @@ def synthesize(
 
     ys.log(f"[INFO] Using SDC file '{sdc_path}' for ABC…")
 
-    if verilog_files := config.get("VERILOG_FILES"):
+    if len(inputs):
+        d.read_verilog_files(
+            inputs,
+            top=config["DESIGN_NAME"],
+            synth_parameters=[],
+            includes=includes,
+            defines=defines,
+            use_synlig=False,
+            synlig_defer=False,
+        )
+    elif verilog_files := config.get("VERILOG_FILES"):
         d.read_verilog_files(
             verilog_files,
             top=config["DESIGN_NAME"],

openlane/steps/pyosys.py

@@ -597,6 +597,30 @@ class Synthesis(SynthesisCommon):
     config_vars = SynthesisCommon.config_vars + verilog_rtl_cfg_vars
 
 
+@Step.factory.register()
+class Resynthesize(SynthesisCommon):
+    """
+    Like ``Synthesis``, but operates on the input netlist instead of RTL files.
+    Useful to process/elaborate on netlists generated by tools other than Yosys.
+
+    Some metrics will also be extracted and updated, namely:
+
+    * ``design__instance__count``
+    * ``design__instance_unmapped__count``
+    * ``design__instance__area``
+    """
+
+    id = "Yosys.Resynthesis"
+    name = "Resynthesis"
+
+    config_vars = SynthesisCommon.config_vars
+
+    inputs = [DesignFormat.NETLIST]
+
+    def get_command(self, state_in):
+        return super().get_command(state_in) + [state_in[DesignFormat.NETLIST]]
+
+
 @Step.factory.register()
 class VHDLSynthesis(SynthesisCommon):
     """