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[rtl] Crop bit width for dynamic selection. #249

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[rtl] Crop bit width for dynamic selection. #249

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4 changes: 2 additions & 2 deletions v/src/Lane.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ case class LaneParameter(
val maskGroupSize: Int = vLen / maskGroupWidth

/** hardware width of [[maskGroupSize]]. */
val maskGroupSizeBits: Int = log2Ceil(maskGroupSize)
val maskGroupSizeBits: Int = log2Ceil(maskGroupSize / laneNumber)

/** Size of the queue for storing execution information
* todo: Determined by the longest execution unit
Expand Down Expand Up @@ -1465,7 +1465,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
val s3Fire = s3Valid && s3Ready
// Used to update valid3 without writing vrf
val s3DequeueFire: Option[Bool] = Option.when(isLastSlot)(Wire(Bool()))
val valid3: Option[Bool] = Option.when(isLastSlot)(RegInit(0.U(false.B)))
val valid3: Option[Bool] = Option.when(isLastSlot)(RegInit(false.B))
// use for cross-lane write
val groupCounterInStage3: Option[UInt] = Option.when(isLastSlot)(RegInit(0.U(7.W)))
val maskInStage3: Option[UInt] = Option.when(isLastSlot)(RegInit(0.U(4.W)))
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4 changes: 2 additions & 2 deletions v/src/V.scala
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Expand Up @@ -642,7 +642,7 @@ class V(val parameter: VParameter) extends Module with SerializableModule[VParam
maskUnitRead.bits.instructionIndex := control.record.instructionIndex
val readResultSelectResult = Mux1H(RegNext(maskUnitReadSelect), laneReadResult)
// 把mask选出来
val maskSelect = v0(groupCounter ## writeBackCounter)
val maskSelect = v0((groupCounter ## writeBackCounter)(log2Ceil(parameter.maskGroupSize) - 1, 0))
val fullMask: UInt = (-1.S(parameter.datapathWidth.W)).asUInt

/** 正常全1
Expand Down Expand Up @@ -808,7 +808,7 @@ class V(val parameter: VParameter) extends Module with SerializableModule[VParam
)
// 对于up来说小于offset的element是不变得的
val slideUpUnderflow = slideUp && !slide1 && (signBit || srcOverlap)
val elementActive: Bool = v0.asUInt(elementIndexCount) || vm
val elementActive: Bool = v0.asUInt(elementIndexCount(log2Ceil(parameter.vLen) - 1, 0)) || vm
val slidActive = elementActive && (!slideUpUnderflow || !decodeResultReg(Decoder.slid))
// index >= vlMax 是写0
val overlapVlMax: Bool = !slideUp && (signBit || srcOversize)
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