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wip purge out tilelink
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@sequencer
sequencer committed Jun 12, 2024
1 parent 5b40478 commit a0de299
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Showing 12 changed files with 57 additions and 302 deletions.
84 changes: 0 additions & 84 deletions configgen/src/Main.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ import chisel3.util.{BitPat, log2Ceil}
import chisel3.util.experimental.BitSet
import mainargs._
import org.chipsalliance.t1.rtl._
import org.chipsalliance.t1.rtl.lsu.LSUInstantiateParameter
import org.chipsalliance.t1.rtl.vrf.RamType
import java.util.LinkedHashMap

Expand Down Expand Up @@ -67,29 +66,6 @@ object Main {
vLen,
dLen,
extensions = Seq("Zve32f"),
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
Seq(
BitSet(BitPat("b01???????????????????????00?????"), BitPat("b10???????????????????????00?????")),
BitSet(BitPat("b01???????????????????????01?????"), BitPat("b10???????????????????????01?????")),
BitSet(BitPat("b01???????????????????????10?????"), BitPat("b10???????????????????????10?????")),
BitSet(BitPat("b01???????????????????????11?????"), BitPat("b10???????????????????????11?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 8banks
Seq(
BitSet(BitPat("b11000000000?????????????000?????")),
BitSet(BitPat("b11000000000?????????????001?????")),
BitSet(BitPat("b11000000000?????????????010?????")),
BitSet(BitPat("b11000000000?????????????011?????")),
BitSet(BitPat("b11000000000?????????????100?????")),
BitSet(BitPat("b11000000000?????????????101?????")),
BitSet(BitPat("b11000000000?????????????110?????")),
BitSet(BitPat("b11000000000?????????????111?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 1,
vrfRamType = RamType.p0rwp1rw,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down Expand Up @@ -138,35 +114,6 @@ object Main {
vLen,
dLen,
extensions = Seq("Zve32x"),
// banks=8 dLen=512 beatbyte16
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
// bp '01???????????????????????00?????'
// base '01000000000000000000000000000000'
// cmask '11000000000000000000000001100000'
// cmaskinv '00111111111111111111111110011111'
// asmask '11000000000000000000000001100000'
Seq(
BitSet(BitPat("b01??????????????????????00??????"), BitPat("b10??????????????????????00??????")),
BitSet(BitPat("b01??????????????????????01??????"), BitPat("b10??????????????????????01??????")),
BitSet(BitPat("b01??????????????????????10??????"), BitPat("b10??????????????????????10??????")),
BitSet(BitPat("b01??????????????????????11??????"), BitPat("b10??????????????????????11??????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 8banks
Seq(
BitSet(BitPat("b11000000000????????????000??????")),
BitSet(BitPat("b11000000000????????????001??????")),
BitSet(BitPat("b11000000000????????????010??????")),
BitSet(BitPat("b11000000000????????????011??????")),
BitSet(BitPat("b11000000000????????????100??????")),
BitSet(BitPat("b11000000000????????????101??????")),
BitSet(BitPat("b11000000000????????????110??????")),
BitSet(BitPat("b11000000000????????????111??????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 2,
vrfRamType = RamType.p0rp1w,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down Expand Up @@ -215,37 +162,6 @@ object Main {
vLen,
dLen,
extensions = Seq("Zve32x"),
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
Seq(
BitSet(BitPat("b01?????????????????????00???????"), BitPat("b10?????????????????????00???????")),
BitSet(BitPat("b01?????????????????????01???????"), BitPat("b10?????????????????????01???????")),
BitSet(BitPat("b01?????????????????????10???????"), BitPat("b10?????????????????????10???????")),
BitSet(BitPat("b01?????????????????????11???????"), BitPat("b10?????????????????????11???????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 16banks
Seq(
BitSet(BitPat("b1100000000?????????0000?????????")),
BitSet(BitPat("b1100000000?????????0001?????????")),
BitSet(BitPat("b1100000000?????????0010?????????")),
BitSet(BitPat("b1100000000?????????0011?????????")),
BitSet(BitPat("b1100000000?????????0100?????????")),
BitSet(BitPat("b1100000000?????????0101?????????")),
BitSet(BitPat("b1100000000?????????0110?????????")),
BitSet(BitPat("b1100000000?????????0111?????????")),
BitSet(BitPat("b1100000000?????????1000?????????")),
BitSet(BitPat("b1100000000?????????1001?????????")),
BitSet(BitPat("b1100000000?????????1010?????????")),
BitSet(BitPat("b1100000000?????????1011?????????")),
BitSet(BitPat("b1100000000?????????1100?????????")),
BitSet(BitPat("b1100000000?????????1101?????????")),
BitSet(BitPat("b1100000000?????????1110?????????")),
BitSet(BitPat("b1100000000?????????1111?????????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 4,
vrfRamType = RamType.p0rw,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down
29 changes: 0 additions & 29 deletions ipemu/src/TestBench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -207,34 +207,5 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
bundle.RREADY
// IP -> Sim

val peek = Module(new PeekAXI(dut.parameter.tlParam.bundle(), latPeekTL))
peek.clock.ref := clockGen.clock
peek.channel.ref := idx.U
peek.aBits_opcode.ref := bundle.a.bits.opcode
peek.aBits_param.ref := bundle.a.bits.param
peek.aBits_size.ref := bundle.a.bits.size
peek.aBits_source.ref := bundle.a.bits.source
peek.aBits_address.ref := bundle.a.bits.address
peek.aBits_mask.ref := bundle.a.bits.mask
peek.aBits_data.ref := bundle.a.bits.data
peek.aBits_corrupt.ref := bundle.a.bits.corrupt

peek.aValid.ref := bundle.a.valid
peek.dReady.ref := bundle.d.ready

val poke = Module(new PokeAXI(dut.parameter.tlParam.bundle(), latPokeTL))
poke.clock.ref := clockGen.clock
poke.channel.ref := idx.U
bundle.d.bits.opcode := poke.dBits_opcode.ref
bundle.d.bits.param := poke.dBits_param.ref
bundle.d.bits.sink := poke.dBits_sink.ref
bundle.d.bits.source := poke.dBits_source.ref
bundle.d.bits.size := poke.dBits_size.ref
bundle.d.bits.denied := poke.dBits_denied.ref
bundle.d.bits.data := poke.dBits_data.ref
bundle.d.bits.corrupt := poke.dBits_corrupt.ref
bundle.d.valid := poke.dValid.ref
poke.dReady.ref := bundle.d.ready
bundle.a.ready := poke.aReady.ref
}
}
16 changes: 1 addition & 15 deletions rocket/src/AbstractT1.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -129,24 +129,10 @@ abstract class AbstractLazyT1()(implicit p: Parameters) extends LazyModule {
def xLen: Int
def vlMax: Int
def uarchName: String
def t1LSUParameters: T1LSUParameter

def bitsetToAddressSet(bitset: BitSet): Seq[AddressSet] = bitset.terms.map(bp => AddressSet(bp.value, bp.mask ^ ((BigInt(1) << bp.width) - 1))).toSeq

val t1LSUNode = TLClientNode(
t1LSUParameters.banks.zipWithIndex.map {
case (addresses, bank) =>
TLMasterPortParameters.v1(
Seq(
TLMasterParameters.v1(
name = s"${uarchName}_bank$bank",
sourceId = IdRange(0, (1 << t1LSUParameters.sourceIdSize) - 1),
visibility = addresses
)
)
)
}
)
val t1LSUNode: TLClientNode = ???
val requestSinkNode: BundleBridgeSink[DecoupledIO[VectorRequest]] =
BundleBridgeSink[DecoupledIO[VectorRequest]]()
val csrSinkNode: BundleBridgeSink[CSRInterface] =
Expand Down
31 changes: 0 additions & 31 deletions subsystem/src/LazyT1.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -22,12 +22,6 @@ class LazyT1()(implicit p: Parameters) extends AbstractLazyT1 {
def uarchName: String = "t1"
def xLen: Int = generator.parameter.xLen
def vlMax: Int = generator.parameter.vLen
override def t1LSUParameters: T1LSUParameter =
T1LSUParameter(
name = generator.parameter.lsuParameters.name,
banks = generator.parameter.lsuParameters.banks.map(bank => bitsetToAddressSet(bank.region)),
sourceIdSize = generator.parameter.sourceWidth
)
}

class LazyT1Imp(outer: LazyT1)(implicit p: Parameters) extends AbstractLazyT1ModuleImp(outer) {
Expand Down Expand Up @@ -88,31 +82,6 @@ class LazyT1Imp(outer: LazyT1)(implicit p: Parameters) extends AbstractLazyT1Mod
// TODO: fixme
t1.storeBufferClear := true.B

// TODO: multiple LSU support
outer.t1LSUNode.out.zipWithIndex.foreach {
case ((bundle, _), i) =>
bundle.a.bits.opcode := t1.memoryPorts(i).a.bits.opcode
bundle.a.bits.param := t1.memoryPorts(i).a.bits.param
bundle.a.bits.size := t1.memoryPorts(i).a.bits.size
bundle.a.bits.source := t1.memoryPorts(i).a.bits.source
bundle.a.bits.address := t1.memoryPorts(i).a.bits.address
bundle.a.bits.mask := t1.memoryPorts(i).a.bits.mask
bundle.a.bits.data := t1.memoryPorts(i).a.bits.data
bundle.a.bits.corrupt := t1.memoryPorts(i).a.bits.corrupt
bundle.a.valid := t1.memoryPorts(i).a.valid
t1.memoryPorts(i).a.ready := bundle.a.ready
t1.memoryPorts(i).d.bits.opcode := bundle.d.bits.opcode
t1.memoryPorts(i).d.bits.param := bundle.d.bits.param
t1.memoryPorts(i).d.bits.size := bundle.d.bits.size
t1.memoryPorts(i).d.bits.source := bundle.d.bits.source
t1.memoryPorts(i).d.bits.sink := bundle.d.bits.sink
t1.memoryPorts(i).d.bits.denied := bundle.d.bits.denied
t1.memoryPorts(i).d.bits.data := bundle.d.bits.data
t1.memoryPorts(i).d.bits.corrupt := bundle.d.bits.corrupt
t1.memoryPorts(i).d.valid := bundle.d.valid
bundle.d.ready := t1.memoryPorts(i).d.ready

}

om := t1.om
}
74 changes: 40 additions & 34 deletions subsystem/src/Subsystem.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ import org.chipsalliance.t1.rockettile.BuildT1
import org.chipsalliance.t1.rtl.{T1, T1OM, T1Parameter}
import chisel3.properties.{Class, ClassType, Path, Property}
import chisel3.util.experimental.BoringUtils.bore
import freechips.rocketchip.amba.axi4.{AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters}


/** The top OM we need to read. */
Expand Down Expand Up @@ -289,10 +290,6 @@ class T1Subsystem(implicit p: Parameters)

// 512M-1G
val scalarMemoryRanges = BitSet(BitPat("b001?????????????????????????????"))
require(
t1Parameter.lsuParameters.banks.filter(_.accessScalar).map(_.region).reduce(_ union _).cover(scalarMemoryRanges),
"Vector accessing scalar should include scalarMemory"
)

// 256M-512M
val mmioRanges = BitSet(BitPat("b0001????????????????????????????"))
Expand All @@ -319,35 +316,46 @@ class T1Subsystem(implicit p: Parameters)
.mkString("")
)

val vectorMemoryNodes = t1Parameter.lsuParameters.banks.filter(!_.accessScalar).map(bank =>
TLManagerNode(
Seq(
TLSlavePortParameters.v1(
Seq(
TLSlaveParameters.v1(
address = bank.region.terms.map(bitsetToAddressSet).toSeq.flatten,
resources = Nil,
regionType = RegionType.UNCACHED,
executable = true,
supportsGet = TransferSizes(1, tlBusWrapperLocationMap(VectorMasterBus).blockBytes),
supportsPutPartial = TransferSizes(1, tlBusWrapperLocationMap(VectorMasterBus).blockBytes),
supportsPutFull = TransferSizes(1, tlBusWrapperLocationMap(VectorMasterBus).blockBytes),
supportsArithmetic = TransferSizes.none,
supportsLogical = TransferSizes.none,
fifoId = Some(0)
)
), // requests are handled in order
// align with datapath size
beatBytes = tlBusWrapperLocationMap(ScalarMasterBus).beatBytes,
minLatency = 1
// TODO: no more diplomacy for boring in and out.
val vectorHighBandwidthNode = AXI4SlaveNode(Seq(
AXI4SlavePortParameters(
slaves = Seq(
AXI4SlaveParameters(
address = Seq(AddressSet.everything),
resources = Nil,
regionType = RegionType.VOLATILE,
executable = false,
nodePath = Nil,
supportsWrite = TransferSizes(4096),
supportsRead = TransferSizes(4096),
// TODO: what's this?
interleavedId = None,
device = None
)
)
),
beatBytes = t1Parameter.dLen / 8,
)
)

vectorMemoryNodes.foreach(vectorMemoryNode =>
tlBusWrapperLocationMap(VectorMasterBus).coupleTo("VectorPort")(vectorMemoryNode := _)
)
))

val vectorIndexedAccessNode = AXI4SlaveNode(Seq(
AXI4SlavePortParameters(
slaves = Seq(
AXI4SlaveParameters(
address = Seq(AddressSet.everything),
resources = Nil,
regionType = RegionType.VOLATILE,
executable = false,
nodePath = Nil,
supportsWrite = TransferSizes(4),
supportsRead = TransferSizes(4),
// TODO: what's this?
interleavedId = None,
device = None
)
),
beatBytes = t1Parameter.dLen / 8,
)
))

// T1 is an accelerator. it only have one scalar outwards bank
val scalarMemoryNode = TLManagerNode(
Expand Down Expand Up @@ -450,9 +458,7 @@ class T1Subsystem(implicit p: Parameters)
}
val scalarPort = InModuleBody { scalarMemoryNode.makeIOs() }
val mmioPort = InModuleBody { mmioNode.makeIOs() }
val vectorPorts = InModuleBody {
vectorMemoryNodes.zipWithIndex.map { case (n, i) => n.makeIOs()(ValName(s"vectorChannel$i")) }
}

private val clockreset = InModuleBody {
val clockInput = clockSource.out.map(_._1).head
val clock = IO(Input(Clock()))
Expand Down
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