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[rtl] switch T1 TileLink to AXI4
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@qinjun-li
qinjun-li committed Jul 5, 2024
1 parent 81907a5 commit 6683274
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84 changes: 0 additions & 84 deletions configgen/src/Main.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,6 @@ import chisel3.util.experimental.BitSet
import mainargs._
import org.chipsalliance.t1.rtl._
import org.chipsalliance.t1.rtl.decoder.T1CustomInstruction
import org.chipsalliance.t1.rtl.lsu.LSUInstantiateParameter
import org.chipsalliance.t1.rtl.vrf.RamType

import java.util.LinkedHashMap
Expand Down Expand Up @@ -70,29 +69,6 @@ object Main {
dLen,
extensions = Seq("Zve32f"),
t1customInstructions = Nil,
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
Seq(
BitSet(BitPat("b01???????????????????????00?????"), BitPat("b10???????????????????????00?????")),
BitSet(BitPat("b01???????????????????????01?????"), BitPat("b10???????????????????????01?????")),
BitSet(BitPat("b01???????????????????????10?????"), BitPat("b10???????????????????????10?????")),
BitSet(BitPat("b01???????????????????????11?????"), BitPat("b10???????????????????????11?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 8banks
Seq(
BitSet(BitPat("b11000000000?????????????000?????")),
BitSet(BitPat("b11000000000?????????????001?????")),
BitSet(BitPat("b11000000000?????????????010?????")),
BitSet(BitPat("b11000000000?????????????011?????")),
BitSet(BitPat("b11000000000?????????????100?????")),
BitSet(BitPat("b11000000000?????????????101?????")),
BitSet(BitPat("b11000000000?????????????110?????")),
BitSet(BitPat("b11000000000?????????????111?????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 1,
vrfRamType = RamType.p0rwp1rw,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down Expand Up @@ -142,35 +118,6 @@ object Main {
dLen,
extensions = Seq("Zve32x"),
t1customInstructions = Nil,
// banks=8 dLen=512 beatbyte16
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
// bp '01???????????????????????00?????'
// base '01000000000000000000000000000000'
// cmask '11000000000000000000000001100000'
// cmaskinv '00111111111111111111111110011111'
// asmask '11000000000000000000000001100000'
Seq(
BitSet(BitPat("b01??????????????????????00??????"), BitPat("b10??????????????????????00??????")),
BitSet(BitPat("b01??????????????????????01??????"), BitPat("b10??????????????????????01??????")),
BitSet(BitPat("b01??????????????????????10??????"), BitPat("b10??????????????????????10??????")),
BitSet(BitPat("b01??????????????????????11??????"), BitPat("b10??????????????????????11??????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 8banks
Seq(
BitSet(BitPat("b11000000000????????????000??????")),
BitSet(BitPat("b11000000000????????????001??????")),
BitSet(BitPat("b11000000000????????????010??????")),
BitSet(BitPat("b11000000000????????????011??????")),
BitSet(BitPat("b11000000000????????????100??????")),
BitSet(BitPat("b11000000000????????????101??????")),
BitSet(BitPat("b11000000000????????????110??????")),
BitSet(BitPat("b11000000000????????????111??????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 2,
vrfRamType = RamType.p0rp1w,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down Expand Up @@ -220,37 +167,6 @@ object Main {
dLen,
extensions = Seq("Zve32x"),
t1customInstructions = Nil,
lsuBankParameters =
// scalar bank 0-1G
Seq(
BitSet(BitPat("b00??????????????????????????????"))
).map(bs => LSUBankParameter("scalar", bs, 8, true)) ++
// ddr bank 1G-3G 512M/bank
Seq(
BitSet(BitPat("b01?????????????????????00???????"), BitPat("b10?????????????????????00???????")),
BitSet(BitPat("b01?????????????????????01???????"), BitPat("b10?????????????????????01???????")),
BitSet(BitPat("b01?????????????????????10???????"), BitPat("b10?????????????????????10???????")),
BitSet(BitPat("b01?????????????????????11???????"), BitPat("b10?????????????????????11???????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"ddrBank$idx", bs, 8, false) } ++
// sRam bank 3G+ 256K/bank, 16banks
Seq(
BitSet(BitPat("b1100000000?????????0000?????????")),
BitSet(BitPat("b1100000000?????????0001?????????")),
BitSet(BitPat("b1100000000?????????0010?????????")),
BitSet(BitPat("b1100000000?????????0011?????????")),
BitSet(BitPat("b1100000000?????????0100?????????")),
BitSet(BitPat("b1100000000?????????0101?????????")),
BitSet(BitPat("b1100000000?????????0110?????????")),
BitSet(BitPat("b1100000000?????????0111?????????")),
BitSet(BitPat("b1100000000?????????1000?????????")),
BitSet(BitPat("b1100000000?????????1001?????????")),
BitSet(BitPat("b1100000000?????????1010?????????")),
BitSet(BitPat("b1100000000?????????1011?????????")),
BitSet(BitPat("b1100000000?????????1100?????????")),
BitSet(BitPat("b1100000000?????????1101?????????")),
BitSet(BitPat("b1100000000?????????1110?????????")),
BitSet(BitPat("b1100000000?????????1111?????????"))
).zipWithIndex.map { case (bs: BitSet, idx: Int) => LSUBankParameter(s"sramBank$idx", bs, 8, false) },
vrfBankSize = 4,
vrfRamType = RamType.p0rw,
vfuInstantiateParameter = VFUInstantiateParameter(
Expand Down
98 changes: 45 additions & 53 deletions t1/src/T1.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,16 +4,16 @@
package org.chipsalliance.t1.rtl

import chisel3._
import chisel3.experimental.hierarchy.{Definition, Instance, Instantiate, instantiable, public}
import chisel3.experimental.hierarchy.{Instance, Instantiate, instantiable, public}
import chisel3.experimental.{SerializableModule, SerializableModuleParameter}
import chisel3.util._
import chisel3.util.experimental.decode._
import tilelink.{TLBundle, TLBundleParameter, TLChannelAParameter, TLChannelDParameter}
import chisel3.probe.{Probe, ProbeValue, define, force}
import chisel3.probe.{Probe, ProbeValue, define}
import chisel3.properties.{AnyClassType, Class, ClassType, Property}
import chisel3.util._
import chisel3.util.experimental.BitSet
import org.chipsalliance.rvdecoderdb.Instruction
import org.chipsalliance.t1.rtl.decoder.{Decoder, DecoderParam, T1CustomInstruction}
import chisel3.util.experimental.decode._
import org.chipsalliance.amba.axi4.bundle.{AXI4BundleParameter, AXI4RWIrrevocable}
import org.chipsalliance.t1.rtl.lsu.{LSU, LSUParameter, LSUProbe}
import org.chipsalliance.t1.rtl.vrf.{RamType, VRFParam, VRFProbe}

Expand Down Expand Up @@ -57,16 +57,6 @@ object T1Parameter {
implicit def rwP: upickle.default.ReadWriter[T1Parameter] = upickle.default.macroRW
}

object LSUBankParameter{
implicit def bitSetP:upickle.default.ReadWriter[BitSet] = upickle.default.readwriter[String].bimap[BitSet](
bs => bs.terms.map("b" + _.rawString).mkString("\n"),
str => BitSet.fromString(str)
)

implicit def rwP: upickle.default.ReadWriter[LSUBankParameter] = upickle.default.macroRW
}
case class LSUBankParameter(name: String, region: BitSet, beatbyte: Int, accessScalar: Boolean)

/**
* @param xLen XLEN
* @param vLen VLEN
Expand All @@ -92,8 +82,6 @@ case class T1Parameter(
dLen: Int,
extensions: Seq[String],
t1customInstructions: Seq[T1CustomInstruction],
// LSU
lsuBankParameters: Seq[LSUBankParameter],
// Lane
vrfBankSize: Int,
vrfRamType: RamType,
Expand All @@ -112,11 +100,6 @@ case class T1Parameter(
case RamType.p0rp1w => "First Port Read, Second Port Write."
case RamType.p0rwp1rw => "Dual Ports Read Write."
}}
|LSU:
|${lsuBankParameters.zipWithIndex.map{case (lsuP, idx) =>
s"""BANK${idx}W${lsuP.beatbyte * 8}b ${if(lsuP.accessScalar) "can" else "can't"} access scalar memory
| ${lsuP.region.terms.map(_.rawString).mkString("\n ")}
|""".stripMargin}}
|""".stripMargin

val allInstructions: Seq[Instruction] = {
Expand Down Expand Up @@ -198,10 +181,6 @@ case class T1Parameter(
/** the hardware width of [[groupNumberMax]]. */
val groupNumberMaxBits: Int = log2Ceil(groupNumberMax)

require(lsuBankParameters.map(_.beatbyte).toSet.size == 1, "The width is temporarily unified")
/** Used in memory bundle parameter. */
val memoryDataWidthBytes: Int = lsuBankParameters.head.beatbyte

/** LSU MSHR Size, Contains a load unit, a store unit and an other unit. */
val lsuMSHRSize: Int = 3

Expand All @@ -218,9 +197,6 @@ case class T1Parameter(
*/
val sizeWidth: Int = log2Ceil(log2Ceil(lsuTransposeSize))

/** for TileLink `mask` element. */
val maskWidth: Int = lsuBankParameters.head.beatbyte

val vrfReadLatency = 2

// each element: Each lane will be connected to the other two lanes,
Expand All @@ -229,13 +205,30 @@ case class T1Parameter(

val decoderParam: DecoderParam = DecoderParam(fpuEnable, allInstructions)

/** parameter for TileLink. */
val tlParam: TLBundleParameter = TLBundleParameter(
a = TLChannelAParameter(physicalAddressWidth, sourceWidth, memoryDataWidthBytes * 8, sizeWidth, maskWidth),
b = None,
c = None,
d = TLChannelDParameter(sourceWidth, sourceWidth, memoryDataWidthBytes * 8, sizeWidth),
e = None
/** paraemter for AXI4. */
val axi4BundleParameter: AXI4BundleParameter = AXI4BundleParameter(
idWidth = sourceWidth,
dataWidth = dLen,
addrWidth = physicalAddressWidth,
userReqWidth = 0,
userDataWidth = 0,
userRespWidth = 0,
hasAW = true,
hasW = true,
hasB = true,
hasAR = true,
hasR = true,
supportId = true,
supportRegion = false,
supportLen = true,
supportSize = true,
supportBurst = true,
supportLock = false,
supportCache = false,
supportQos = false,
supportStrb = true,
supportResp = true,
supportProt = false,
)

/** Parameter for [[Lane]] */
Expand Down Expand Up @@ -263,15 +256,13 @@ case class T1Parameter(
sourceWidth = sourceWidth,
sizeWidth = sizeWidth,
// TODO: configurable for each LSU [[p.supportMask]]
maskWidth = maskWidth,
banks = lsuBankParameters,
maskWidth = dLen / 32,
lsuMSHRSize = lsuMSHRSize,
// TODO: make it configurable for each lane
toVRFWriteQueueSize = 96,
transferSize = lsuTransposeSize,
vrfReadLatency = vrfReadLatency,
// TODO: configurable for each LSU
tlParam = tlParam,
axi4BundleParameter = axi4BundleParameter,
name = "main"
)
def vrfParam: VRFParam = VRFParam(vLen, laneNumber, datapathWidth, chainingSize, vrfBankSize, vrfRamType)
Expand Down Expand Up @@ -303,23 +294,28 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
* and the `kill` logic in Vector processor is too high,
* thus the request should come from commit stage to avoid any interrupt or excepiton.
*/
@public
val request: DecoupledIO[VRequest] = IO(Flipped(Decoupled(new VRequest(parameter.xLen))))

/** response to CPU. */
@public
val response: ValidIO[VResponse] = IO(Valid(new VResponse(parameter.xLen)))

/** CSR interface from CPU. */
@public
val csrInterface: CSRInterface = IO(Input(new CSRInterface(parameter.laneParam.vlMaxBits)))

/** from CPU LSU, store buffer is cleared, memory can observe memory requests after this is asserted. */
@public
val storeBufferClear: Bool = IO(Input(Bool()))

/** TileLink memory ports. */
val memoryPorts: Vec[TLBundle] = IO(Vec(parameter.lsuBankParameters.size, parameter.tlParam.bundle()))

// TODO: expose region name here.
@public
val highBandwidthLoadStorePort: AXI4RWIrrevocable = IO(new AXI4RWIrrevocable(parameter.axi4BundleParameter))
@public
val indexedLoadStorePort: AXI4RWIrrevocable = IO(new AXI4RWIrrevocable(parameter.axi4BundleParameter.copy(dataWidth=32)))
// TODO: this is an example of adding a new Probe
@public
val lsuProbe = IO(Probe(new LSUProbe(parameter.lsuParameters)))
@public
val laneProbes = Seq.tabulate(parameter.laneNumber)(laneIdx => IO(Probe(new LaneProbe(parameter.chainingSize))).suggestName(s"lane${laneIdx}Probe"))
@public
val laneVrfProbes = Seq.tabulate(parameter.laneNumber)(laneIdx => IO(Probe(new VRFProbe(
parameter.laneParam.vrfParam.regNumBits,
parameter.laneParam.vrfOffsetBits,
Expand Down Expand Up @@ -1602,12 +1598,8 @@ class T1(val parameter: T1Parameter) extends Module with SerializableModule[T1Pa
}
}

memoryPorts.zip(lsu.tlPort).foreach {
case (source, sink) =>
val dBuffer = Queue(source.d, 1, flow = true)
sink <> source
sink.d <> dBuffer
}
highBandwidthLoadStorePort <> lsu.axi4Port
indexedLoadStorePort <> lsu.simpleAccessPorts
// 暂时直接连lsu的写,后续需要处理scheduler的写
vrfWrite.zip(lsu.vrfWritePort).foreach { case (sink, source) => sink <> source }

Expand Down
45 changes: 40 additions & 5 deletions t1/src/lsu/Bundle.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,11 +41,6 @@ class SimpleAccessStatus(laneNumber: Int) extends LSUBaseStatus {
val isIndexLS: Bool = Bool()
}

class StoreStatus(bankSize: Int) extends LSUBaseStatus {
// cache line 的发送不能被打断
val releasePort: Vec[Bool] = Vec(bankSize, Bool())
}

class MSHRStage0Bundle(param: MSHRParam) extends Bundle {
// 读的相关
val readVS: UInt = UInt(param.regNumBits.W)
Expand All @@ -69,3 +64,43 @@ class SimpleAccessStage1(param: MSHRParam) extends Bundle {
val address: UInt = UInt(param.paWidth.W)
val readData: UInt = UInt(param.datapathWidth.W)
}

class MemRequest(param: MSHRParam) extends Bundle {
val src: UInt = UInt(param.cacheLineIndexBits.W)
val address: UInt = UInt(param.paWidth.W)
}

class MemDataBundle(param: MSHRParam) extends Bundle {
// todo: DLEN?
val data: UInt = UInt((param.lsuTransposeSize * 8).W)
val index: UInt = UInt(param.cacheLineIndexBits.W)
}

class MemWrite(param: MSHRParam) extends Bundle {
// todo: DLEN?
val data: UInt = UInt((param.lsuTransposeSize * 8).W)
val mask: UInt = UInt(param.lsuTransposeSize.W)
val index: UInt = UInt(param.cacheLineIndexBits.W)
val address: UInt = UInt(param.paWidth.W)
}

class SimpleMemRequest(param: MSHRParam) extends Bundle {
val address: UInt = UInt(param.paWidth.W)
val size: UInt = UInt(2.W)
val source: UInt = UInt(8.W)
}

class SimpleMemReadResponse(param: MSHRParam) extends Bundle {
// todo: DLEN?
val data: UInt = UInt((param.lsuTransposeSize * 8).W)
val source: UInt = UInt(8.W)
}

class SimpleMemWrite(param: MSHRParam) extends Bundle {
// todo: DLEN?
val data: UInt = UInt((param.lsuTransposeSize * 8).W)
val mask: UInt = UInt(param.lsuTransposeSize.W)
val source: UInt = UInt(8.W)
val address: UInt = UInt(param.paWidth.W)
val size: UInt = UInt(2.W)
}
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