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Bulk connection emission for <> fails for "input" wires #4218

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jackkoenig opened this issue Jun 25, 2024 · 0 comments · Fixed by #4219
Closed

Bulk connection emission for <> fails for "input" wires #4218

jackkoenig opened this issue Jun 25, 2024 · 0 comments · Fixed by #4219

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@jackkoenig
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jackkoenig commented Jun 25, 2024

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Consider the following Chisel:

//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.4.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class MyBundle extends Bundle {
  val foo = Input(UInt(8.W))
}

class Foo extends Module {
  val producer = IO(Flipped(new MyBundle))
  val consumer = IO(new MyBundle)

  val w1, w2 = Wire(new MyBundle)
  w1 <> producer
  w2 <> w1
  consumer <> w2
}

object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      gen = new Foo,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}

What is the current behavior?

This fails with:

Exception in thread "main" chisel3.package$ChiselException: Connection between left (Foo.w2: Wire[MyBundle]) and source (Foo.w1: Wire[MyBundle]) failed @.foo: Locally unclear whether Left or Right (both internal)

Now this seems obvious. Of course it fails, it has always failed for <> of wires right? Wellllll sort of. The special emission of FIRRTL bulk connect when possible actually makes this legal if val foo were Flipped instead of Input, and user code relies on this behavior sometimes. The reason is an overly pessimistic check here [1] that should only care about direction being Input if the sink is a port (so the fix is super easy).

I wouldn't bother even reporting this but #4205 exposes some cases because it means the Bundle with Flipped now has Input direction (whereas previously it incorrectly had Bidirectional(_) direction.

What is the expected behavior?

This connection should work to prevent #4205 from breaking things.

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?

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