Merge pull request intel#197 from intel/SPR_metric_correction

Correcting typo on SPR metric "into"->"info"
captain5050 · Jun 10, 2024 · a2b594f · a2b594f
2 parents b4fd1be + 8cf26b7
commit a2b594f
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/SPR/metrics/perf/sapphirerapids_metrics_perf.json b/SPR/metrics/perf/sapphirerapids_metrics_perf.json
@@ -1301,7 +1301,7 @@
     },
     {
         "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor",
-        "MetricExpr": "tma_into_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1",
+        "MetricExpr": "tma_info_thread_slots / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1",
         "MetricGroup": "SMT;TmaL1;TopdownL1;tma_L1_group;Metric",
         "MetricName": "tma_info_thread_slots_utilization"
     },

diff --git a/SPR/metrics/sapphirerapids_metrics.json b/SPR/metrics/sapphirerapids_metrics.json
@@ -2,7 +2,7 @@
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
     "Info": "Performance Monitoring Metrics for 4th Generation Intel(R) Xeon(R) Processor Scalable Family based on Sapphire Rapids microarchitecture0",
-    "DatePublished": "05/14/2024",
+    "DatePublished": "06/07/2024",
     "Version": "0",
     "Legend": "",
     "TmaVersion": "4.8",
@@ -9300,7 +9300,7 @@
         }
       ],
       "Formula": "( a ) / ( b / 2 ) if smt_on else 1",
-      "BaseFormula": " tma_into_thread_slots / ( topdown.slots:percore / 2 ) if smt_on else 1",
+      "BaseFormula": "tma_info_thread_slots / ( topdown.slots:percore / 2 ) if smt_on else 1",
       "Category": "TMA",
       "CountDomain": "Metric",
       "Threshold": {