Merge pull request intel#155 from edwarddavidbaker/sync-platforms

EMR, SPR, ICX, SNR, EHL: Release event updates
captain5050 · Mar 18, 2024 · 1d6efb7 · 1d6efb7
2 parents a4203d3 + 6f67405
commit 1d6efb7
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Showing 14 changed files with 1,239 additions and 3,383 deletions.
diff --git a/EHL/events/elkhartlake_core.json b/EHL/events/elkhartlake_core.json
diff --git a/EMR/events/emeraldrapids_core.json b/EMR/events/emeraldrapids_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.03",
-    "DatePublished": "01/19/2024",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.06",
+    "DatePublished": "03/14/2024",
+    "Version": "1.06",
     "Legend": ""
   },
   "Events": [
@@ -2612,7 +2612,7 @@
       "UMask": "0x08",
       "EventName": "IDQ.DSB_CYCLES_OK",
       "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
-      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
+      "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
       "Counter": "0,1,2,3",
       "PEBScounters": "0,1,2,3",
       "SampleAfterValue": "2000003",
@@ -4802,13 +4802,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",
@@ -4828,13 +4828,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",
@@ -4854,13 +4854,13 @@
       "SampleAfterValue": "2000003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",
@@ -6518,13 +6518,13 @@
       "SampleAfterValue": "100003",
       "MSRIndex": "0x00",
       "MSRValue": "0x00",
-      "Precise": "0",
+      "Precise": "1",
       "CollectPEBSRecord": "2",
       "TakenAlone": "0",
       "CounterMask": "0",
       "Invert": "0",
       "EdgeDetect": "0",
-      "PEBS": "0",
+      "PEBS": "1",
       "Data_LA": "0",
       "L1_Hit_Indication": "0",
       "Errata": "null",

diff --git a/EMR/events/emeraldrapids_uncore.json b/EMR/events/emeraldrapids_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2024 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.03",
-    "DatePublished": "01/19/2024",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for 5th Generation Intel(R) Xeon(R) Processor Scalable Family - V1.06",
+    "DatePublished": "03/14/2024",
+    "Version": "1.06",
     "Legend": ""
   },
   "Events": [
@@ -2571,7 +2571,7 @@
       "FCMask": "0x00",
       "UMaskExt": "0x00cc43fe",
       "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
-      "BriefDescription": "TOR Inserts; ItoM misses from local IO",
+      "BriefDescription": "TOR Inserts : ItoM, indicating a full cacheline write request, from IO Devices that missed the LLC",
       "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
       "Counter": "0,1,2,3",
       "ELLC": "0",
@@ -3849,7 +3849,7 @@
       "FCMask": "0x00",
       "UMaskExt": "0x00c8f3fe",
       "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
-      "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO",
+      "BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from local IO that miss LLC",
       "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
       "Counter": "0,1,2,3",
       "ELLC": "0",
@@ -5028,6 +5028,114 @@
       "Deprecated": "0",
       "FILTER_VALUE": "0",
       "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00C8F2FF",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
+      "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
+      "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00C8F37F",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
+      "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
+      "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00CC437F",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
+      "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket",
+      "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00CC42FF",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
+      "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket",
+      "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00CD437F",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
+      "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket",
+      "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
+    },
+    {
+      "Unit": "CHA",
+      "EventCode": "0x35",
+      "UMask": "0x04",
+      "PortMask": "0x00",
+      "FCMask": "0x00",
+      "UMaskExt": "0x00CD42FF",
+      "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
+      "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket",
+      "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.   Does not include addressless requests such as locks and interrupts.",
+      "Counter": "0,1,2,3",
+      "ELLC": "0",
+      "Filter": "na",
+      "ExtSel": "0",
+      "Deprecated": "0",
+      "FILTER_VALUE": "0",
+      "CounterType": "PGMABLE"
     }
   ]
 }