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Instructor: 劉建男
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Prerequisites: C++, Introduction to digital systems and VLSI design
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Course descriptions and objectives:
Computer-aided design (CAD) techniques are essential for modern complex designs. In this course, the CAD techniques for the synthesis and verification of VLSI designs are introduced. Besides using those CAD tools, our focus is the insight techniques and algorithms to develop the synthesis and verification tools. These contents are important background knowledge to do the related researches. For those students whose research directions are not CAD-related topics, better understanding of CAD tools also helps to use those tools better.
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Scoring:
- 3 assignments (40%)
- midterm exam (30%)
- final exam (30%)
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Reference Books:
- Giovanni De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994.
- Prakash Rashinkar, Peter Paterson, and Leena Singh, "System-on-a-chip Verification – Methodology and Techniques", Kluwer Academic Publishers, 2001.
- L.-T. Wang, Y.-W. Chang, and K.-T. Cheng, "Electronic Design Automation: Synthesis, Verification, and Testing", Elsevier/Morgan Kaufmann, 2009.
Week | Date | Course Progress | Assignment |
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1 | 20240710 | Binary decision diagram (BDD) | |
1 | 20240712 | RTL synthesis & logic optimization | |
2 | 20240717 | RTL synthesis & logic optimization | |
2 | 20240719 | System-level low-power design techniques | |
3 | 20240724 | Technology mapping & timing optimization | |
3 | 20240726 | Technology mapping & timing optimization | Lab1 start |
4 | 20240731 | Verification methodology for SoC | |
4 | 20240802 | Coverage-driven functional verification methodology | |
5 | 20240807 | Formal verification techniques | |
5 | 20240809 | Midterm Exam | Lab1 end/ Lab2 srart |
6 | 20240814 | Analog/mixed-signal system verification | |
6 | 20240816 | Analog/mixed-signal system verification | |
7 | 20240821 | Analog/mixed-signal system verification | |
7 | 20240823 | Synthesis of analog circuits | |
7 | 20240826 | Lab3 start | |
8 | 20240828 | Synthesis of analog circuits | Lab2 end |
8 | 20240830 | Final Exam | |
8 | 20240831 | Lab3 end |