static-timing-analysis

Here are 14 public repositories matching this topic...

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated May 26, 2023
Verilog

clin99 / awesome-eda

Star

open-source parser fpga simulation timer routing verification eda verilog circuit systemverilog gds logic-synthesis lithography placement static-timing-analysis

Updated Jun 26, 2019

OpenTimer / Parser-SPEF

Star

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Aug 7, 2022
C++

fayizferosh / yosys-tcl-ui-report

Star

5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

MalakSadek / StaticTimingAnalyzer

Star

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

python c html json graph-algorithms scl verilog logic-gates verilog-hdl logic-circuit static-timing-analysis

Updated Mar 25, 2021
HTML

Randy1005 / Ink

Star

Incremental k-Critical Path Generation

graph static-timing-analysis

Updated Apr 2, 2024
C++

Visruat / VSD-TCL

Star

TCL Script automating the frontend of ASIC design

tcl synthesis static-timing-analysis asic-design

Updated Jun 21, 2023
Verilog

kanndil / PathView

Star

An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.

eda primetime critical-path-analysis pathview static-timing-analysis opensta schematic-layout electronic-design

Updated Oct 22, 2024
HTML

Crepopcorn / sta_check_temporary

Star

This project is the script for STA report violated path checks temporarily (not final version due to confidentiality).

python c testing linux shell bash perl bash-script checking static-timing-analysis

Updated Oct 16, 2024
C

coherent17 / NYCU-Special-Topics-in-Computer-Aided-Design

Star

CAD in NYCU

quine-mccluskey-algorithm static-timing-analysis power-analyzer mix-signal-simulation

Updated Dec 22, 2023
Verilog

shobhit-mittra / STA-Review

Star

This project is a part of the report for my 7th semester program elective (EC-4143 VLSI-CAD).

analysis tcl eda verilog static-timing-analysis prime-time open-timer

Updated Jan 11, 2024
Tcl

YubiYubi719 / NYCU-Special-Topics-in-Computer-Aided-Design

Star

quine-mccluskey cad quine-mccluskey-algorithm static-timing-analysis

Updated Sep 19, 2024
Verilog

Pa1mantri / TCL_Workshop

Star

5-Day TCL begginer to advanced workshop by VSD

linux open-source tcl synthesis yosys hardware-description-language static-timing-analysis tcl-procedures opentimer

Updated Jan 24, 2024
Verilog

RustamC / rsta

Star

Rust bindings for OpenSTA

rust eda sta static-timing-analysis

Updated Sep 6, 2023
Rust

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static-timing-analysis

Here are 14 public repositories matching this topic...

OpenTimer / OpenTimer

clin99 / awesome-eda

OpenTimer / Parser-SPEF

fayizferosh / yosys-tcl-ui-report

MalakSadek / StaticTimingAnalyzer

Randy1005 / Ink

Visruat / VSD-TCL

kanndil / PathView

Crepopcorn / sta_check_temporary

coherent17 / NYCU-Special-Topics-in-Computer-Aided-Design

shobhit-mittra / STA-Review

YubiYubi719 / NYCU-Special-Topics-in-Computer-Aided-Design

Pa1mantri / TCL_Workshop

RustamC / rsta

Improve this page

Add this topic to your repo