chore: update version

TerosTechnology · Jul 17, 2023 · 82b076a · 82b076a
1 parent 41625fc
commit 82b076a
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Showing 3 changed files with 4 additions and 3 deletions.
diff --git a/packages/teroshdl/auto_package/templates/info.nj b/packages/teroshdl/auto_package/templates/info.nj
@@ -2,7 +2,7 @@
 "displayName": "TerosHDL",
 "publisher": "teros-technology",
 "description": "Powerful IDE for ASIC/FPGA: state machine viewer, linter, documentation, snippets... and more! ",
-"version": "5.0.4",
+"version": "5.0.5",
 "engines": {
     "vscode": "^1.74.0"
 },

diff --git a/packages/teroshdl/package.json b/packages/teroshdl/package.json
@@ -3,7 +3,7 @@
     "displayName": "TerosHDL",
     "publisher": "teros-technology",
     "description": "Powerful IDE for ASIC/FPGA: state machine viewer, linter, documentation, snippets... and more! ",
-    "version": "5.0.4",
+    "version": "5.0.5",
     "engines": {
         "vscode": "^1.74.0"
     },

diff --git a/packages/teroshdl/resources/release_notes/release-notes.html b/packages/teroshdl/resources/release_notes/release-notes.html
@@ -33,13 +33,14 @@
     <br>
     <br>
 
-    <h4 id="release-notes"> Minor changes v5.0.4</h4>
+    <h4 id="release-notes"> Minor changes v5.0.4 and v5.0.5</h4>
     <p>
         <ul>
             <li> Support for GUI in VUnit</li>
             <li> Support for "copy as VHDL component" in Verilog/SV templates</li>
             <li> Fix bug parsing Verilog/SV arrays</li>
             <li> Fix bug updating VHDL libraries</li>
+            <li> Fix bug in linter when path has white space</li>
         </ul>
     </p>