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181 Open 274 Closed
181 Open 274 Closed
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Issues list

Indentation following vhdl 'when' clause bug Something isn't working
#678 opened Oct 2, 2024 by SittingDuc
1
Failed to access library 'C:\Users\namhe\.teroshdl_fryIl_' at "C:\Users\namhe\.teroshdl_fryIl_".TerosHDL: modelsim(vlog-19) bug Something isn't working
#677 opened Oct 1, 2024 by FinnNGrace
Quartus path resolution incorrect for windows, SILENT fallback to QUARTUS_ROOTDIR bug Something isn't working
#671 opened Sep 27, 2024 by dbee-novosound
2
Q: TerosHDL and Python virtual environments bug Something isn't working
#660 opened Sep 17, 2024 by mkaiser
3
Schematic viewer with GHDL/Yosys cannot find work lib bug Something isn't working
#659 opened Sep 14, 2024 by atticlabsdesign
2
Error when trying to instantiate an entity containing a generic type (VHDL 2008) bug Something isn't working
#658 opened Sep 10, 2024 by vdahle
VHDL comment type for Verilog testbench template bug Something isn't working
#656 opened Sep 5, 2024 by SebekO
Support for inline if statement in state machine viewer enhancement New feature or request
#655 opened Sep 5, 2024 by SebekO
Update/Upload TerosHDL on OpenVSX enhancement New feature or request
#654 opened Sep 5, 2024 by gfcwfzkm
32
Format selection (VHDL, possibly other languages as well) enhancement New feature or request
#653 opened Sep 4, 2024 by ckuhlmann
Add **Chinese** language support enhancement New feature or request
#643 opened Aug 21, 2024 by miilTgy
1
Support for specific VUnit project enhancement New feature or request
#641 opened Aug 15, 2024 by james-ziegler
5
[FEATURE REQUEST]: Update XDC language for more highlights enhancement New feature or request
#640 opened Aug 8, 2024 by wimille
1
Comment/Description for Last Signal Missing in Module documentation bug Something isn't working
#637 opened Jul 23, 2024 by jchang-endiag
VHDL 2008 Block Comment End Characters Appear in Documentation enhancement New feature or request
#636 opened Jul 23, 2024 by jchang-endiag
1
[GHDL / Modelsim] Simulation fails if path contains whitespaces bug Something isn't working
#635 opened Jul 15, 2024 by gfcwfzkm
Wrong port direction in Module documentation when `ifdef enhancement New feature or request
#631 opened Jun 27, 2024 by niciki-niciki
1
The autocomplete suggestion does not work for unsaved files. enhancement New feature or request
#630 opened Jun 27, 2024 by narutozxp
1
Schematic generation successfulness depends on project file order if libraries are used bug Something isn't working
#628 opened Jun 19, 2024 by ila-embsys
3
SystemVerilog package import support enhancement New feature or request
#626 opened Jun 19, 2024 by gtaylormb
2
Feature: Format selection enhancement New feature or request
#625 opened Jun 19, 2024 by ckuhlmann
Schematic viewer dosen't work bug Something isn't working
#624 opened Jun 19, 2024 by deleteTh
25
Error schematic generation if top units more than one on VHDL files bug Something isn't working
#614 opened May 20, 2024 by ila-embsys
2
Go to definition doesn’t work bug Something isn't working
#611 opened May 3, 2024 by NickTxD
1
Vending_Machine bug Something isn't working
#608 opened Apr 19, 2024 by FinnNGrace
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