ЛР2. Исправление подключения АЛУ в nexys_alu

MPSU · Sep 19, 2023 · 004b2c3 · 004b2c3
1 parent 99c429b
commit 004b2c3
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
@@ -26,12 +26,12 @@ reg minus;
 
 alu_riscv DUT
 (
-  .ALUOp  (operator_i),
-  .A      (operand_a_i),
-  .B      (operand_b_i),
+  .alu_op_i (operator_i),
+  .a_i      (operand_a_i),
+  .b_i      (operand_b_i),
 
-  .Result (result_o),
-  .Flag   (comparison_result_o)
+  .result_o (result_o),
+  .flag_o   (comparison_result_o)
 );
 
 assign operator_i  = SW[4:0];
@@ -93,4 +93,4 @@ always @(posedge CLK100) begin
     end
 end
 
-endmodule
+endmodule