i#6662 public traces, part 1: synthetic ISA

api/docs/release.dox

@@ -217,6 +217,10 @@ Further non-compatibility-affecting changes include:
    is set to true by default to match the existing behavior of the invariant checker.
  - Added a new instr API instr_is_xrstor() that tells whether an instruction is any
    variant of the x86 xrstor opcode.
+ - Added a new #dr_isa_mode_t: #DR_ISA_REGDEPS, which is a synthetic ISA with the main
+   purpose of preserving register dependencies.
+ - Added instr_convert_to_isa_regdeps() API that converts an #instr_t from a real ISA
+   (e.g., #DR_ISA_AMD64) to the #DR_ISA_REGDEPS synthetic ISA.
 
 **************************************************
 <hr>

core/CMakeLists.txt

@@ -279,6 +279,8 @@ set(DECODER_SRCS
   ir/${ARCH_NAME}/decode.c
   ir/encode_shared.c
   ir/${ARCH_NAME}/encode.c
+  ir/isa_regdeps/encode.c
+  ir/isa_regdeps/decode.c
   ir/disassemble_shared.c
   ir/${ARCH_NAME}/disassemble.c
   ir/ir_utils_shared.c

core/ir/aarch64/codec.c

@@ -40,9 +40,11 @@
 
 #include <stdint.h>
 #include "../globals.h"
+#include "../isa_regdeps/decode.h"
 #include "arch.h"
 #include "decode.h"
 #include "disassemble.h"
+#include "encode_api.h"
 #include "instr.h"
 #include "instr_create_shared.h"
 
@@ -9717,6 +9719,14 @@ decode_category(uint encoding, instr_t *instr)
 byte *
 decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
 {
+    /* #DR_ISA_REGDEPS synthetic ISA has its own decoder.
+     * XXX i#1684: when DR can be built with full dynamic architecture selection we won't
+     * need to pollute the decoding of other architectures with this synthetic ISA special
+     * case.
+     */
+    if (dr_get_isa_mode(dcontext) == DR_ISA_REGDEPS)
+        return decode_isa_regdeps(dcontext, pc, instr);
+
     byte *next_pc = pc + 4;
     uint enc = *(uint *)pc;
     uint eflags = 0;

core/ir/aarch64/decode.c

@@ -32,6 +32,7 @@
  */
 
 #include "../globals.h"
+#include "encode_api.h"
 #include "instr.h"
 #include "decode.h"
 #include "decode_fast.h" /* ensure we export decode_next_pc, decode_sizeof */
@@ -41,7 +42,7 @@
 bool
 is_isa_mode_legal(dr_isa_mode_t mode)
 {
-    return (mode == DR_ISA_ARM_A64);
+    return (mode == DR_ISA_ARM_A64 || mode == DR_ISA_REGDEPS);
 }
 
 app_pc

core/ir/aarch64/instr.c

@@ -45,9 +45,9 @@
 bool
 instr_set_isa_mode(instr_t *instr, dr_isa_mode_t mode)
 {
-    if (mode != DR_ISA_ARM_A64)
+    if (mode != DR_ISA_ARM_A64 && mode != DR_ISA_REGDEPS)
         return false;
-    instr->isa_mode = DR_ISA_ARM_A64;
+    instr->isa_mode = mode;
     return true;
 }
 

core/ir/arm/decode.c

@@ -31,6 +31,8 @@
  */
 
 #include "../globals.h"
+#include "../isa_regdeps/decode.h"
+#include "encode_api.h"
 #include "instr.h"
 #include "decode.h"
 #include "decode_private.h"
@@ -172,7 +174,7 @@ decode_in_it_block(decode_state_t *state, app_pc pc, decode_info_t *di)
 bool
 is_isa_mode_legal(dr_isa_mode_t mode)
 {
-    return (mode == DR_ISA_ARM_THUMB || DR_ISA_ARM_A32);
+    return (mode == DR_ISA_ARM_THUMB || mode == DR_ISA_ARM_A32 || mode == DR_ISA_REGDEPS);
 }
 
 /* We need to call canonicalize_pc_target() on all next_tag-writing
@@ -2428,6 +2430,14 @@ decode_opcode(dcontext_t *dcontext, byte *pc, instr_t *instr)
 static byte *
 decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
 {
+    /* #DR_ISA_REGDEPS synthetic ISA has its own decoder.
+     * XXX i#1684: when DR can be built with full dynamic architecture selection we won't
+     * need to pollute the decoding of other architectures with this synthetic ISA special
+     * case.
+     */
+    if (dr_get_isa_mode(dcontext) == DR_ISA_REGDEPS)
+        return decode_isa_regdeps(dcontext, pc, instr);
+
     const instr_info_t *info = &invalid_instr;
     decode_info_t di;
     byte *next_pc;

core/ir/arm/instr.c

@@ -43,7 +43,7 @@
 bool
 instr_set_isa_mode(instr_t *instr, dr_isa_mode_t mode)
 {
-    if (mode != DR_ISA_ARM_THUMB && mode != DR_ISA_ARM_A32) {
+    if (mode != DR_ISA_ARM_THUMB && mode != DR_ISA_ARM_A32 && mode != DR_ISA_REGDEPS) {
         return false;
     }
     instr->isa_mode = mode;

core/ir/encode_api.h

@@ -51,6 +51,38 @@ typedef enum _dr_isa_mode_t {
     DR_ISA_ARM_THUMB,         /**< Thumb (ARM T32). */
     DR_ISA_ARM_A64,           /**< ARM A64 (AArch64). */
     DR_ISA_RV64IMAFDC,        /**< RISC-V (rv64imafdc). */
+    DR_ISA_REGDEPS,
+    /**<
+     * This is a synthetic ISA that has the purpose of preserving register dependencies
+     * and giving hints on the type of operations each instruction is performing.
+     *
+     * For this reason the majority of operations that would normally work on instructions
+     * coming from an actual ISA (e.g., #DR_ISA_AMD64) are not supported.
+     *
+     * Currently we support:
+     * - instr_convert_to_isa_regdeps(), which converts an #instr_t of an actual ISA to a
+     *   #DR_ISA_REGDEPS instruction;
+     * - instr_encode() and instr_encode_to_copy(), to encode a #DR_ISA_REGDEPS #instr_t
+     *   into a sequence of contiguous bytes;
+     * - decode() and decode_from_copy(), to decode an encoded #DR_ISA_REGDEPS instruction
+     *   into an #instr_t.
+     *
+     * A #DR_ISA_REGDEPS #instr_t holds only the encoded information described in the
+     * encoding scheme, which is:
+     * - categories (from #dr_instr_category_t), to indicate the type of operation
+     *   performed (e.g., load, store, floating point math operation, branch, etc.);
+     * - arithmetic flags, with no distinction between different flags, we only report if
+     *   at least one flag was read and/or written;
+     * - number of source and destination register operands;
+     * - operation size;
+     * - list of register operand identifiers, separated in source and destination;
+     * - ISA mode, which is #DR_ISA_REGDEPS.
+     *
+     * Querying additional information (e.g., the instruction opcode) will return the
+     * default value generated by how the instruction was created.  If instr_create() was
+     * used, then zero will be returned.  If the #instr_t was allocated on the stack, then
+     * all values not described above are undefined.
+     */
 } dr_isa_mode_t;
 
 DR_API

core/ir/encode_shared.c

@@ -38,6 +38,7 @@
 /* encode_shared.c -- cross-platform encodingn routines */
 
 #include "../globals.h"
+#include "isa_regdeps/encode.h"
 #include "arch.h"
 #include "instr.h"
 #include "decode.h"
@@ -131,6 +132,15 @@ byte *
 instr_encode_to_copy(void *drcontext, instr_t *instr, byte *copy_pc, byte *final_pc)
 {
     dcontext_t *dcontext = (dcontext_t *)drcontext;
+
+    /* #DR_ISA_REGDEPS synthetic ISA has its own encoder.
+     * XXX i#1684: when DR can be built with full dynamic architecture selection we won't
+     * need to pollute the encoding of other architectures with this synthetic ISA special
+     * case.
+     */
+    if (instr_get_isa_mode(instr) == DR_ISA_REGDEPS)
+        return encode_isa_regdeps(dcontext, instr, copy_pc);
+
     return instr_encode_arch(dcontext, instr, copy_pc, final_pc, true,
                              NULL _IF_DEBUG(true));
 }

core/ir/instr_api.h

@@ -298,10 +298,14 @@ struct _instr_t {
 
     uint opcode;
 
-#    ifdef X86
-    /* PR 251479: offset into instr's raw bytes of rip-relative 4-byte displacement */
-    byte rip_rel_pos;
-#    endif
+    union {
+        /* PR 251479: offset into instr's raw bytes of rip-relative 4-byte displacement */
+        byte rip_rel_pos;
+        /* PR #6691: size of source data (i.e., read) an instruction operates on.
+         * Note that opnd_size_t is an alias for byte.
+         */
+        opnd_size_t operation_size;
+    };
 
     /* we dynamically allocate dst and src arrays b/c x86 instrs can have
      * up to 8 of each of them, but most have <=2 dsts and <=3 srcs, and we
@@ -2095,6 +2099,21 @@ DR_API
 instr_t *
 instr_convert_short_meta_jmp_to_long(void *drcontext, instrlist_t *ilist, instr_t *instr);
 
+DR_API
+/**
+ * Converts a real ISA (e.g., #DR_ISA_AMD64) instruction \p instr_real_isa into a
+ * #DR_ISA_REGDEPS instruction and stores it into \p instr_regdeps_isa.
+ * Assumes \p instr_regdeps_isa has been allocated by the caller (e.g., using
+ * instr_create()).
+ * Assumes \p instr_real_isa is a fully-decoded or synthesized instruction of a real ISA
+ * with valid operand information.
+ * \note \p instr_regdeps_isa will contain only the information of a #DR_ISA_REGDEPS
+ * synthetic instruction.
+ */
+void
+instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
+                             instr_t *instr_regdeps_isa);
+
 DR_API
 /**
  * Given \p eflags, returns whether or not the conditional branch, \p

core/ir/instr_shared.c

@@ -52,6 +52,7 @@
 #define INSTR_INLINE extern inline
 
 #include "../globals.h"
+#include "isa_regdeps/encoding_common.h"
 #include "instr.h"
 #include "arch.h"
 #include "../link.h"
@@ -2999,6 +3000,142 @@ instr_uses_fp_reg(instr_t *instr)
     return false;
 }
 
+void
+instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
+                             instr_t *instr_regdeps_isa)
+{
+    /* Retrieve number of register destination operands from real ISA instruction.
+     * Note that a destination operand that is a memory renference should have its
+     * registers (if any) counted as source operands, since they are being read.
+     * We use [src|dst]_reg_used to keep track of registers we've seen and avoid
+     * duplicates.
+     */
+    bool src_reg_used[MAX_NUM_REGS];
+    memset(src_reg_used, 0, sizeof(src_reg_used));
+    uint num_srcs = 0;
+    bool dst_reg_used[MAX_NUM_REGS];
+    memset(dst_reg_used, 0, sizeof(dst_reg_used));
+    uint num_dsts = 0;
+    uint instr_real_num_dsts = (uint)instr_num_dsts(instr_real_isa);
+    for (uint dst_index = 0; dst_index < instr_real_num_dsts; ++dst_index) {
+        opnd_t dst_opnd = instr_get_dst(instr_real_isa, dst_index);
+        uint num_regs_used_by_opnd = (uint)opnd_num_regs_used(dst_opnd);
+        if (opnd_is_memory_reference(dst_opnd)) {
+            for (uint opnd_index = 0; opnd_index < num_regs_used_by_opnd; ++opnd_index) {
+                reg_id_t reg = opnd_get_reg_used(dst_opnd, opnd_index);
+                /* Map sub-registers to their containing register.
+                 */
+                reg_id_t reg_canonical = reg_to_pointer_sized(reg);
+                if (!src_reg_used[reg_canonical]) {
+                    ++num_srcs;
+                    src_reg_used[reg_canonical] = true;
+                }
+            }
+        } else {
+            for (uint opnd_index = 0; opnd_index < num_regs_used_by_opnd; ++opnd_index) {
+                reg_id_t reg = opnd_get_reg_used(dst_opnd, opnd_index);
+                /* Map sub-registers to their containing register.
+                 */
+                reg_id_t reg_canonical = reg_to_pointer_sized(reg);
+                if (!dst_reg_used[reg_canonical]) {
+                    ++num_dsts;
+                    dst_reg_used[reg_canonical] = true;
+                }
+            }
+        }
+    }
+
+    /* Retrieve number of register source operands from real ISA instruction.
+     * We use max_src_opnd_size_bytes to keep track of the size of the largest source
+     * operand.
+     * We count the number of bytes instead of using opnd_size_t to avoid relying on
+     * OPSZ_ enum values.
+     * We convert max_src_opnd_size_bytes to its corresponding OPSZ_ enum value later on,
+     * and store it into operation_size.
+     */
+    uint max_src_opnd_size_bytes = 0;
+    uint instr_real_num_srcs = (uint)instr_num_srcs(instr_real_isa);
+    for (uint i = 0; i < instr_real_num_srcs; ++i) {
+        opnd_t src_opnd = instr_get_src(instr_real_isa, i);
+        opnd_size_t opnd_size = opnd_get_size(src_opnd);
+        uint opnd_size_bytes = opnd_size_in_bytes(opnd_size);
+        if (opnd_size_bytes > max_src_opnd_size_bytes)
+            max_src_opnd_size_bytes = opnd_size_bytes;
+        uint num_regs_used_by_opnd = (uint)opnd_num_regs_used(src_opnd);
+        for (uint opnd_index = 0; opnd_index < num_regs_used_by_opnd; ++opnd_index) {
+            reg_id_t reg = opnd_get_reg_used(src_opnd, opnd_index);
+            /* Map sub-registers to their containing register.
+             */
+            reg_id_t reg_canonical = reg_to_pointer_sized(reg);
+            if (!src_reg_used[reg_canonical]) {
+                ++num_srcs;
+                src_reg_used[reg_canonical] = true;
+            }
+        }
+    }
+
+    /* Declare num of source and destination operands valid in the converted instruction.
+     */
+    instr_set_num_opnds(drcontext, instr_regdeps_isa, num_dsts, num_srcs);
+
+    /* Retrieve arithmetic flags from real ISA instruction.
+     * If the real ISA instruction reads or writes one or more arithmetic flag, all
+     * arithmetic flags will be set to read or written in the converted instruction.
+     * Note that this operation can trigger additional encoding and decoding of
+     * instr_real_isa, depending on its decoding level.
+     */
+    uint eflags_instr_real = instr_get_arith_flags(instr_real_isa, DR_QUERY_DEFAULT);
+    uint eflags_instr_regdeps = 0;
+    if (TESTANY(EFLAGS_WRITE_ARITH, eflags_instr_real))
+        eflags_instr_regdeps |= EFLAGS_WRITE_ARITH;
+    if (TESTANY(EFLAGS_READ_ARITH, eflags_instr_real))
+        eflags_instr_regdeps |= EFLAGS_READ_ARITH;
+    instr_regdeps_isa->eflags = eflags_instr_regdeps;
+    instr_set_arith_flags_valid(instr_regdeps_isa, true);
+
+    /* Retrieve category of real ISA instruction and set it directly as the category of
+     * the converted instruction.  No changes needed here.
+     */
+    instr_set_category(instr_regdeps_isa, instr_get_category(instr_real_isa));
+
+    /* Convert max_src_opnd_size_bytes from number of bytes to opnd_size_t (which holds
+     * OPSZ_ enum values).
+     */
+    instr_regdeps_isa->operation_size = opnd_size_from_bytes(max_src_opnd_size_bytes);
+
+    /* Set the source and destination register operands for the converted instruction.
+     */
+    if (num_dsts > 0) {
+        uint reg_counter = 0;
+        for (uint reg = 0; reg < MAX_NUM_REGS; ++reg) {
+            if (dst_reg_used[reg]) {
+                opnd_t dst_opnd = opnd_create_reg((reg_id_t)reg);
+                instr_set_dst(instr_regdeps_isa, reg_counter, dst_opnd);
+                ++reg_counter;
+            }
+        }
+    }
+
+    if (num_srcs > 0) {
+        uint reg_counter = 0;
+        for (uint reg = 0; reg < MAX_NUM_REGS; ++reg) {
+            if (src_reg_used[reg]) {
+                opnd_t src_opnd = opnd_create_reg((reg_id_t)reg);
+                instr_set_src(instr_regdeps_isa, reg_counter, src_opnd);
+                ++reg_counter;
+            }
+        }
+    }
+
+    /* Declare converted instruction operands to be valid.
+     */
+    instr_set_operands_valid(instr_regdeps_isa, true);
+
+    /* Set converted instruction ISA mode to be DR_ISA_REGDEPS.
+     */
+    instr_set_isa_mode(instr_regdeps_isa, DR_ISA_REGDEPS);
+}
+
 /* We place these here rather than in mangle_shared.c to avoid the work of
  * linking mangle_shared.c into drdecodelib.
  */