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i#6662 public traces, part 1: synthetic ISA #6691

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Apr 10, 2024
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f9bebe0
i#6662 synthetic ISA: encoding
edeiana Feb 28, 2024
4b70a9d
Forgot to include encode header for synthetic ISA.
edeiana Feb 28, 2024
d301f3e
Added synthetic encoding header to CMakeList.
edeiana Feb 29, 2024
a0bbf6f
Added initial implementation of synthetic encoding/decoding.
edeiana Mar 6, 2024
8b29dcc
Using x86 encode/decode for synthetic encoding/decoding
edeiana Mar 6, 2024
d2115e6
Added test for synthetic encoding/decoding.
edeiana Mar 6, 2024
44c4c3c
Merge branch 'master' into i6662-synthetic-isa
edeiana Mar 6, 2024
246003c
Added encoding/deconding of operands, although virtual registers
edeiana Mar 15, 2024
85ac64d
Fixed description of synthetic ISA mode.
edeiana Mar 15, 2024
79b736b
Updated uses of spelled out DR_ISA_SYNTHETIC.
edeiana Mar 15, 2024
9e67807
Merge remote-tracking branch 'origin/master' into i6662-synthetic-isa
edeiana Mar 15, 2024
1e8a686
Updated synthetic ISA enum use.
edeiana Mar 15, 2024
8bc947a
Updated test for synthetic ISA encoding/decoding.
edeiana Mar 15, 2024
df82fcf
Now returning next instruction's PC after synthetic ISA
edeiana Mar 15, 2024
21e8d77
Improved description in comment.
edeiana Mar 15, 2024
b3cac08
Fixed building error.
edeiana Mar 15, 2024
89e80d7
clang-format.
edeiana Mar 15, 2024
b4b1fd8
Addressed memory alignment, eflags, constants, description of encoding.
edeiana Mar 18, 2024
8df36c1
Fixed minosr issue in Synthetic ISA test: merged lines.
edeiana Mar 18, 2024
dc5f750
Setting instr_t length according to the size of the synthetic
edeiana Mar 20, 2024
8400177
Now considering registers in destination operands that are memory
edeiana Mar 20, 2024
d346c27
Improved test.
edeiana Mar 20, 2024
8d63bbf
Check for instr_t synthetic ISA moved to instr_encode()
edeiana Mar 20, 2024
4787fad
We want to minimize the impact of synthetic ISA.
edeiana Mar 20, 2024
978ed90
Now setting arithetic, operand, and raw bits flags valid after decoding.
edeiana Mar 20, 2024
efc6cf2
We don't need to temporarly change instr_t ISA mode to retrieve flags
edeiana Mar 20, 2024
46bacdb
Documented that we use instr_t ISA mode for decoding when
edeiana Mar 20, 2024
9c96008
Now checking flags, instr length, and PC.
edeiana Mar 20, 2024
615d55f
Fixed "warning C4018: '<': signed/unsigned mismatch" treated
edeiana Mar 20, 2024
df3c68d
Fixed __attribute__ extention not supported by our windows compiler.
edeiana Mar 20, 2024
dd5a979
Whoops, forgot to zero-out the first 4 bytes before encoding.
edeiana Mar 20, 2024
d4f1b3e
Improved comments.
edeiana Mar 21, 2024
7a95872
Now using dcontext ISA mode for decoding in x86.
edeiana Mar 21, 2024
806a72c
Moved encode_to_synth() from instr_encode() to instr_encode_to_copy().
edeiana Mar 21, 2024
e13b25b
Using local variable for header bytes of encoding, instead of
edeiana Mar 21, 2024
ef8560c
Improved description.
edeiana Mar 21, 2024
ab65804
Addressed PR comments.
edeiana Mar 21, 2024
b1bd6d5
Fixed grammar.
edeiana Mar 21, 2024
23995d3
Added decode_from_synth() into decode() of every architecture.
edeiana Mar 22, 2024
b1f844a
Removed synthetic ISA related tests from ir_x86.c set of tests.
edeiana Mar 22, 2024
ce3c5e1
Fixed AARCH64 and RISCV64 tests.
edeiana Mar 22, 2024
0e318dd
Added DR_ISA_SYNTHETIC to is_isa_mode_legal() for all arches.
edeiana Mar 22, 2024
224fadf
Removed decode_from_synth() from decode_from_copy(), we only want it in
edeiana Mar 22, 2024
ddf7b10
Now allowing DR_ISA_SYNTHETIC for all arches in instr_set_isa_mode().
edeiana Mar 22, 2024
363ef2e
Fixed ARM 32 test.
edeiana Mar 22, 2024
c29f344
Addressed misc (mostly minor) review comments.
edeiana Mar 23, 2024
1a2a6b1
Mapping sub-registers to their canonical register (i.e., the largest …
edeiana Mar 24, 2024
035d014
Fixed register size encoding.
edeiana Mar 24, 2024
6d4d4cf
Check if src or dst operands are present before looping through
edeiana Mar 24, 2024
96133f8
Biggest encoded synthetis instruction is now 20 bytes.
edeiana Mar 24, 2024
91981df
Fixed offset when encoding/decoding src operands.
edeiana Mar 24, 2024
bc22a59
Moved decode_from_synth() from decode() to decode_common() for all
edeiana Mar 26, 2024
2856ab0
Now we only have a single operation size field (1 byte encoding).
edeiana Mar 26, 2024
70f6942
Fix building errors for aarch64 and riscv64.
edeiana Mar 26, 2024
4caf3aa
Fix failure on AARCH64.
edeiana Mar 27, 2024
9bc4a80
Fix building error (typo).
edeiana Mar 27, 2024
f88f9b2
Renamed DR_ISA_SYNTHETIC to DR_ISA_REGDEPS.
edeiana Mar 27, 2024
a9ff2d5
Forgot one DR_ISA_SYNTHETIC in aarch64. Fixed.
edeiana Mar 27, 2024
5cd8856
Added instr_convert_to_isa_regdeps() API to translate an instr_t
edeiana Mar 29, 2024
cc34ec5
Added new API to release doc.
edeiana Mar 29, 2024
87d60ab
Updated tests.
edeiana Mar 29, 2024
ef7554c
Minor cleanup.
edeiana Mar 29, 2024
9e7c7f8
Merge branch 'master' into i6662-synthetic-isa
edeiana Mar 29, 2024
3d0106f
clang-format-14 run.
edeiana Mar 29, 2024
4553779
Fixed warning as error on windows.
edeiana Mar 29, 2024
55f737c
Added #mem_ops (i.e., loads + stores) to encoding.
edeiana Mar 31, 2024
f05c367
Added a couple more x86 instructions to test with implicit
edeiana Mar 31, 2024
2374332
Increased size of array containing encoding to max encoding size of 16
edeiana Mar 31, 2024
1b01ed5
Reverted back to no #mem_ops.
edeiana Apr 2, 2024
28b779a
Added DR_ISA_REGDEPS description.
edeiana Apr 4, 2024
c284c6b
Changed convert_to_isa_regdeps() signature.
edeiana Apr 4, 2024
9d785e1
Removed unnecessary cast to (void *).
edeiana Apr 4, 2024
a7149e9
Renaming: from synthetic to isa_regdeps.
edeiana Apr 5, 2024
547d39b
Renaming: encoding/decoding functions using isa_regdeps name.
edeiana Apr 5, 2024
2a0ada8
Added operation_size, modified encoding/decoding accordingly.
edeiana Apr 6, 2024
0b58ad7
Improved description of encoding scheme and its readability.
edeiana Apr 6, 2024
e67df8a
Improved test.
edeiana Apr 6, 2024
d41e21e
Updated documentation.
edeiana Apr 7, 2024
8db9a06
Fixed typo in documentation.
edeiana Apr 7, 2024
4615d17
clang-format-14 run.
edeiana Apr 7, 2024
8d08c07
clang-format-14 run, again.
edeiana Apr 7, 2024
cefaba5
Added encode + decode of instructions generated by INSTR_CREATE_.
edeiana Apr 7, 2024
2b0ad5e
Removed INSTR_CREATE_adr from tests for aarch64 because of i#4847.
edeiana Apr 7, 2024
d125010
Removed setting of instr_t.length, we don't use it anymore,
edeiana Apr 7, 2024
be82357
Updated test's expected output.
edeiana Apr 7, 2024
e639309
Added instr_encode_common() with is now the common routine interposed
edeiana Apr 8, 2024
b29d8a1
Added valid encoding to bytes field of instr_t when converting and
edeiana Apr 9, 2024
74c681f
Formatting fixed.
edeiana Apr 9, 2024
b931392
Addressed PR feedback.
edeiana Apr 9, 2024
1340b90
Fromatting fixed.
edeiana Apr 9, 2024
0d57ec9
Removed unnecessary header.
edeiana Apr 9, 2024
1c828b8
Improved comments and code documentation (doxygen).
edeiana Apr 9, 2024
5ad7405
Merge branch 'master' into i6662-synthetic-isa
edeiana Apr 9, 2024
2aad8e0
Fixed doxygen. Cannot reference #DR_ISA_REGDEPS in a pre-comment for
edeiana Apr 9, 2024
01ef05c
Trying to fix doxygen.
edeiana Apr 10, 2024
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2 changes: 2 additions & 0 deletions core/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -279,6 +279,8 @@ set(DECODER_SRCS
ir/${ARCH_NAME}/decode.c
ir/encode_shared.c
ir/${ARCH_NAME}/encode.c
ir/synthetic/encode.c
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ir/synthetic/decode.c
ir/disassemble_shared.c
ir/${ARCH_NAME}/disassemble.c
ir/ir_utils_shared.c
Expand Down
1 change: 1 addition & 0 deletions core/ir/encode_api.h
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ typedef enum _dr_isa_mode_t {
DR_ISA_ARM_THUMB, /**< Thumb (ARM T32). */
DR_ISA_ARM_A64, /**< ARM A64 (AArch64). */
DR_ISA_RV64IMAFDC, /**< RISC-V (rv64imafdc). */
DR_ISA_SYNTH, /**< Synthetic ISA for public traces. */
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} dr_isa_mode_t;

DR_API
Expand Down
6 changes: 6 additions & 0 deletions core/ir/instr.h
Original file line number Diff line number Diff line change
Expand Up @@ -215,6 +215,12 @@ enum {
#endif
/* PR 267260: distinguish our own mangling from client-added instrs */
INSTR_OUR_MANGLING = 0x80000000,
/*
* Synthetic ISA mode.
* TOFIX: we're exceeding 4 bytes, this is an issue on 32 bits arch
* where uint flags of instr_t is only 4 bytes.
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*/
INSTR_SYNTH_MODE = 0x100000000,
};

#define DR_TUPLE_TYPE_BITS 4
Expand Down
93 changes: 93 additions & 0 deletions core/ir/synthetic/decode.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
/* **********************************************************
* Copyright (c) 2011-2024 Google, Inc. All rights reserved.
* Copyright (c) 2001-2010 VMware, Inc. All rights reserved.
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* **********************************************************/

/*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of VMware, Inc. nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
/* Copyright (c) 2003-2007 Determina Corp. */
/* Copyright (c) 2001-2003 Massachusetts Institute of Technology */
/* Copyright (c) 2001 Hewlett-Packard Company */

/* decode.c -- a decoder for DR synthetic IR */

#include "encode.h"
#include "decode.h"

#include "../globals.h"
#include "instr_api.h"

#define CATEGORY_BITS 22
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#define FLAGS_BITS 2
#define NUM_OPND_BITS 4

void
decode_from_synth(dcontext_t *dcontext, byte *encoded_instr, instr_t *instr)
{
uint encoding = 0;
uint shift = 0;

/*
* Copy encoded_instr in a uint for easy retrieving of values.
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*/
memcpy(&encoding, encoded_instr, sizeof(uint));
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/*
* Decode synthetic opcode as instruction category.
*/
uint category_mask = (1U << CATEGORY_BITS) - 1;
uint category = encoding & category_mask;
instr_set_category(instr, category);
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shift += CATEGORY_BITS;

/*
* Decode flags.
*/
// Commented to avoid unused variable error.
// uint flags_mask = ((1U << FLAGS_BITS) - 1) << shift;
// uint flags = encoding & flags_mask;
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// TOFIX: set all arithmetic flags of instr_t?
shift += FLAGS_BITS;

/*
* Decode number of source operands.
*/
uint num_srcs_mask = ((1U << NUM_OPND_BITS) - 1) << shift;
uint num_srcs = encoding & num_srcs_mask;
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shift += NUM_OPND_BITS;

/*
* Decode number of destination operands.
*/
uint num_dsts_mask = ((1U << NUM_OPND_BITS) - 1) << shift;
uint num_dsts = encoding & num_dsts_mask;
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instr_set_num_opnds(dcontext, instr, num_dsts, num_srcs);

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return;
}
9 changes: 9 additions & 0 deletions core/ir/synthetic/decode.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
#ifndef _SYNTHETIC_DECODE_H_
#define _SYNTHETIC_DECODE_H_ 1

#include "../globals.h"

void
decode_from_synth(dcontext_t *dcontext, byte *encoded_instr, instr_t *instr);

#endif /* _SYNTHETIC_DECODE_H_ */
91 changes: 91 additions & 0 deletions core/ir/synthetic/encode.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,91 @@
/* **********************************************************
* Copyright (c) 2011-2024 Google, Inc. All rights reserved.
* Copyright (c) 2001-2010 VMware, Inc. All rights reserved.
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* **********************************************************/

/*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of VMware, Inc. nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
/* Copyright (c) 2003-2007 Determina Corp. */
/* Copyright (c) 2001-2003 Massachusetts Institute of Technology */
/* Copyright (c) 2001 Hewlett-Packard Company */

/* encode.c -- an encoder for DR synthetic IR */

#include "encode.h"

#include "../globals.h"

#define CATEGORY_BITS 22
#define FLAGS_BITS 2
#define NUM_OPND_BITS 4

void
encode_to_synth(dcontext_t *dcontext, instr_t *instr, byte *encoded_instr)
{
uint encoding = 0;
uint shift = 0;

/*
* Encode category as synthetic opcode.
*/
uint category = instr_get_category(instr);
encoding |= category;
shift += CATEGORY_BITS;

/*
* Encode flags.
*/
// TOFIX: this is probably not the right way to look at arithmetic flags of an instr_t
uint flags = (uint)instr_arith_flags_valid(instr);
encoding |= (flags << shift);
shift += FLAGS_BITS;

/*
* Encode number of source operands.
*/
uint num_srcs = (uint)instr_num_srcs(instr);
encoding |= (num_srcs << shift);
shift += NUM_OPND_BITS;

/*
* Encode number of destination operands.
*/
uint num_dsts = (uint)instr_num_dsts(instr);
encoding |= (num_dsts << shift);

/*
* TODO: Encode registers.
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*/

/*
* Copy result to output encoded_instr.
*/
memcpy(encoded_instr, &encoding, sizeof(uint));
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return;
}
9 changes: 9 additions & 0 deletions core/ir/synthetic/encode.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
#ifndef _SYNTHETIC_ENCODE_H_
#define _SYNTHETIC_ENCODE_H_ 1

#include "../globals.h"

void
encode_to_synth(dcontext_t *dcontext, instr_t *instr, byte *encoded_instr);

#endif /* _SYNTHETIC_ENCODE_H_ */
11 changes: 11 additions & 0 deletions core/ir/x86/decode.c
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
/* decode.c -- a full x86 decoder */

#include "../globals.h"
#include "../synthetic/decode.h"
#include "arch.h"
#include "instr.h"
#include "decode.h"
Expand Down Expand Up @@ -2579,6 +2580,16 @@ check_is_variable_size(opnd_t op)
static byte *
decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
{
/*
* If we're dealing with decoding from synthetic ISA, we don't care about returning
* the pc of the next instruction (?), so we just write the encoding in final_pc and
* return it.
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*/
if (instr_get_isa_mode(instr) == DR_ISA_SYNTH) {
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decode_from_synth(dcontext, orig_pc, instr);
return orig_pc;
}

const instr_info_t *info;
decode_info_t di;
byte *next_pc;
Expand Down
11 changes: 11 additions & 0 deletions core/ir/x86/encode.c
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
/* encode.c -- an x86 encoder */

#include "../globals.h"
#include "../synthetic/encode.h"
#include "arch.h"
#include "instr.h"
#include "decode.h"
Expand Down Expand Up @@ -2759,6 +2760,16 @@ instr_encode_arch(dcontext_t *dcontext, instr_t *instr, byte *copy_pc, byte *fin
bool *has_instr_opnds /*OUT OPTIONAL*/
_IF_DEBUG(bool assert_reachable))
{
/*
* If we're dealing with encoding to synthetic ISA, we don't care about returning
* the pc of the next instruction (?), so we just write the encoding in final_pc and
* return it.
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*/
if (instr_get_isa_mode(instr) == DR_ISA_SYNTH) {
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encode_to_synth(dcontext, instr, final_pc);
return final_pc;
}

const instr_info_t *info;
decode_info_t di;

Expand Down
8 changes: 8 additions & 0 deletions core/ir/x86/instr.c
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@
#include "instr.h"
#include "decode.h"
#include "decode_private.h"
#include "encode_api.h"
#include "instr_create_shared.h"

#ifdef X64
Expand Down Expand Up @@ -70,6 +71,10 @@ instr_get_x86_mode(instr_t *instr)
bool
instr_set_isa_mode(instr_t *instr, dr_isa_mode_t mode)
{
if (mode == DR_ISA_SYNTH) {
instr->flags |= INSTR_SYNTH_MODE;
return true;
}
#ifdef X64
if (mode == DR_ISA_IA32)
instr_set_x86_mode(instr, true);
Expand All @@ -87,6 +92,9 @@ instr_set_isa_mode(instr_t *instr, dr_isa_mode_t mode)
dr_isa_mode_t
instr_get_isa_mode(instr_t *instr)
{
if (TEST(INSTR_SYNTH_MODE, instr->flags)) {
return DR_ISA_SYNTH;
}
#ifdef X64
return TEST(INSTR_X86_MODE, instr->flags) ? DR_ISA_IA32 : DR_ISA_AMD64;
#else
Expand Down
42 changes: 42 additions & 0 deletions suite/tests/api/ir_x86.c
Original file line number Diff line number Diff line change
Expand Up @@ -787,6 +787,46 @@ test_instr_encode_and_decode(void *dc, instr_t *instr, uint len_expect,
instr_destroy(dc, decin);
}

bool
instr_same_synthetic(instr_t *inst1, instr_t *inst2)
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{
if (instr_num_srcs(inst1) != instr_num_srcs(inst2))
return false;

if (instr_num_dsts(inst1) != instr_num_dsts(inst2))
return false;

if (instr_get_isa_mode(inst1) != instr_get_isa_mode(inst2))
return false;

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return true;
}

static void
test_instr_encode_decode_synthetic(void *dc, instr_t *instr, byte *bytes)
{
instr_t *instr_copy;
instr_set_isa_mode(instr, DR_ISA_SYNTH);
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instr_encode(dc, instr, bytes);
instr_copy = instr_create(dc);
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instr_set_isa_mode(instr_copy, DR_ISA_SYNTH);
decode(dc, bytes, instr_copy);
ASSERT(instr_same_synthetic(instr, instr_copy));
instr_destroy(dc, instr);
instr_destroy(dc, instr_copy);
}

static void
test_instr_create_encode_decode_synthetic(void *dc)
{
instr_t *instr;
opnd_t abs_addr = opnd_create_abs_addr((void *)0xdeadbeefdeadbeef, OPSZ_8);

instr = INSTR_CREATE_mov_ld(dc, opnd_create_reg(DR_REG_RAX), abs_addr);
byte bytes[8];
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test_instr_encode_decode_synthetic(dc, instr, bytes);
}

static void
test_indirect_cti(void *dc)
{
Expand Down Expand Up @@ -2879,6 +2919,8 @@ main(int argc, char *argv[])
dr_mutex_destroy(x);
#endif

test_instr_create_encode_decode_synthetic(dcontext);

test_all_opcodes_0(dcontext);
#ifndef STANDALONE_DECODER /* speed up compilation */
test_all_opcodes_1(dcontext);
Expand Down
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