Specify FST for Verilator dump

zeroasiccorp · Nov 7, 2023 · 98cc556 · 98cc556
1 parent 262997f
commit 98cc556
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Showing 2 changed files with 3 additions and 2 deletions.
diff --git a/examples/umiram/test.py b/examples/umiram/test.py
@@ -101,7 +101,8 @@ def build_testbench(fast=False):
         dut.add('option', option, EX_DIR / 'deps' / 'umi' / 'umi' / 'rtl')
 
     # Settings
-    dut.set('option', 'trace', True)  # enable VCD (TODO: FST option)
+    dut.set('option', 'trace', True)
+    dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')
 
     result = None
 

diff --git a/examples/umiram/testbench.sv b/examples/umiram/testbench.sv
@@ -66,7 +66,7 @@ module testbench (
 
     initial begin
         if ($test$plusargs("trace")) begin
-            $dumpfile("testbench.vcd");
+            $dumpfile("testbench.fst");
             $dumpvars(0, testbench);
         end
     end