soc: boards: Add Mediatek MT8186 and MT8188 audio DSPs #74352
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This is currently selected by the arch, but some devices (in paticular xtensa ones which have configurable interrupt setups) might not actually be able to effect an irq_offload() from within an ISR even though we have code for it. Make this a default and not a select so that lower layers can override the setting. Signed-off-by: Andy Ross <[email protected]>
Wire the default printk output to the console at boot, just to be sure we have stdio output good enough to get tests to pass. Signed-off-by: Andy Ross <[email protected]>
This is a feature of the 8195 DSP only, which is used only vestigially by SOF to store data that nothing reads. The Linux kernel on the other side uses a shared driver for all 81xx devices, which does not expose the feature. It seems to work, but it's not worth maintaining a driver in tree for legacy hardware that will never use it. Signed-off-by: Andy Ross <[email protected]>
These are very similar devices to mt8195, minimal changes needed beyond boilerplate configuration. Note that the cpuclk driver is not yet ported, it works only with 8195 (the clocking/power architecture seems similar between the parts, but the graph of wells and clocks is different and historically these have been three separate drivers in SOF). The biggest changes are in the image/loader scripts, which needed some rework for cross-device portability. Signed-off-by: Andy Ross <[email protected]>
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Simple docs for this board family. Not a lot of complexity currently. Signed-off-by: Andy Ross <[email protected]>
nordicjm
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Jul 1, 2024
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config BOARD_MT8186_ADSP | ||
| bool "Mediatek MT8186 Audio DSP" |
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| bool "Mediatek MT8186 Audio DSP" |
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config BOARD_MT8188_ADSP | ||
| bool "Mediatek MT8188 Audio DSP" |
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| bool "Mediatek MT8188 Audio DSP" |
| @@ -3,3 +3,4 @@ | |||
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| config BOARD_MT8195_ADSP | |||
| bool "Mediatek MT8195 Audio DSP" | |||
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| bool "Mediatek MT8195 Audio DSP" |
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| # Copyright 2024 The ChromiumOS Authors | |||
| # SPDX-License-Identifier: Apache-2.0 | |||
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| config SOC_FAMILY_MTK_ADSP | |||
| bool "Mediatek MT8xxx Series Audio DSPs" | |||
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| bool "Mediatek MT8xxx Series Audio DSPs" | |
| bool |
| bool "Mediatek MT8xxx Series Audio DSPs" | ||
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| config SOC_SERIES_MT8195_ADSP | ||
| bool "Mediatek 8195 Audio DSP" |
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| bool "Mediatek 8195 Audio DSP" | |
| bool |
| Mediatek MT8195 Audio DSP | ||
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| config SOC_SERIES_MT818X_ADSP | ||
| bool "Mediatek 818x Audio DSPs" |
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| bool "Mediatek 818x Audio DSPs" | |
| bool |
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These are very similar devices to mt8195, minimal changes needed beyond boilerplate configuration.
See notes in commit messages. Also note that this requires the HAL commit in zephyrproject-rtos/hal_xtensa#30 , I know there's a convention for including cross-repo PR west updates for build purposes, but given that the RFC is about to be cut I think this can probably just wait for the HAL merge. There's no rush to get it in prior to the freeze anyway.