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xtensa: add support for dc233c SoC for QEMU
This adds SoC and board configs to support the dc233c core that is available on QEMU. This core has more features than sample_controller, such as MMU support. Signed-off-by: Daniel Leung <[email protected]>
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# XTENSA board configuration | ||
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# Copyright (c) 2017 Intel Corporation | ||
# Copyright (c) 2017, 2023 Intel Corporation | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config BOARD_QEMU_XTENSA | ||
bool "Xtensa emulation using QEMU" | ||
depends on SOC_XTENSA_SAMPLE_CONTROLLER | ||
select QEMU_TARGET | ||
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config BOARD_QEMU_XTENSA_DC233C | ||
bool "Xtensa emulation using QEMU (dc233c core)" | ||
depends on SOC_XTENSA_DC233C | ||
select QEMU_TARGET |
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/* | ||
* Copyright (c) 2019, 2023 Intel Corporation. | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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/dts-v1/; | ||
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#include "dc233c.dtsi" | ||
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/ { | ||
model = "qemu_xtensa_dc233c"; | ||
compatible = "cdns,xtensa-dc233c"; | ||
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chosen { | ||
zephyr,sram = &sram0; | ||
}; | ||
}; | ||
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&cpu0 { | ||
clock-frequency = <10000000>; | ||
}; |
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identifier: qemu_xtensa_dc233c | ||
name: QEMU Emulation for Xtensa (dc233c core) | ||
type: qemu | ||
simulation: qemu | ||
arch: xtensa | ||
toolchain: | ||
- xtools | ||
testing: | ||
ignore_tags: | ||
- net | ||
- bluetooth |
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# SPDX-License-Identifier: Apache-2.0 | ||
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CONFIG_MAIN_STACK_SIZE=2048 | ||
CONFIG_BOARD_QEMU_XTENSA_DC233C=y | ||
CONFIG_CONSOLE=y | ||
CONFIG_SOC_XTENSA_DC233C=y | ||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 | ||
CONFIG_STACK_SENTINEL=y | ||
CONFIG_GEN_ISR_TABLES=y | ||
CONFIG_GEN_IRQ_VECTOR_TABLE=n | ||
CONFIG_SIMULATOR_XTENSA=y | ||
CONFIG_QEMU_ICOUNT_SHIFT=6 |
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/* | ||
* Copyright (c) 2023 Intel Corporation. | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include "skeleton.dtsi" | ||
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/ { | ||
cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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cpu0: cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "cdns,tensilica-xtensa-lx3"; | ||
reg = <0>; | ||
}; | ||
}; | ||
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/* | ||
* Although RAM is of size 128MB (0x08000000), limit this to 16MB so | ||
* fewer L2 page table entries are needed when MMU is enabled. | ||
*/ | ||
sram0: memory@00000000 { | ||
device_type = "memory"; | ||
compatible = "mmio-sram"; | ||
reg = <0x00000000 0x01000000>; | ||
}; | ||
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/* | ||
* Although ROM is of size 32MB (0x02000000), limit this to 8KB so | ||
* fewer L2 page table entries are needed when MMU is enabled. | ||
*/ | ||
rom0: memory@fe000000 { | ||
device_type = "memory"; | ||
compatible = "mmio-sram"; | ||
reg = <0xfe000000 0x00002000>; | ||
}; | ||
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soc { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
compatible = "simple-bus"; | ||
ranges; | ||
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}; | ||
}; |
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# SPDX-License-Identifier: Apache-2.0 | ||
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zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU mmu.c) |
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# Copyright (c) 2016 Open-RnD Sp. z o.o. | ||
# Copyright (c) 2016 Cadence Design Systems, Inc. | ||
# Copyright (c) 2023 Intel Corporation | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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if SOC_XTENSA_DC233C | ||
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config SOC | ||
default "dc233c" | ||
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config SOC_TOOLCHAIN_NAME | ||
string | ||
default "dc233c" | ||
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config XTENSA_MMU_NUM_L2_TABLES | ||
int | ||
default 48 if XTENSA_MMU | ||
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# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB. | ||
# This is to allow VECBASE to be mapped permanently | ||
# via TLB way 4 (which covers 1MB). | ||
config SRAM_OFFSET | ||
hex | ||
default 0x100000 | ||
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config KERNEL_VM_OFFSET | ||
hex | ||
default 0x100000 | ||
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endif |
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# Copyright (c) 2017, 2023 Intel Corporation | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config SOC_XTENSA_DC233C | ||
bool "Xtensa dc233c core" | ||
select XTENSA | ||
select XTENSA_HAL | ||
select CPU_HAS_MMU | ||
imply XTENSA_MMU | ||
select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU |
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