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zephyr: remove intel_s1000 and add dc233c #22

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Aug 26, 2023
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zephyr: remove intel_s1000 and add dc233c #22

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05ab24c
zephyr: remove intel_s1000
dcpleung Aug 16, 2023
620ccf8
hal: fix uninitialized variable warning in xthal_v2p()
dcpleung Aug 16, 2023
66c4ac1
xtensa: add config and overlay for dc233c core
dcpleung Aug 15, 2023
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2 changes: 1 addition & 1 deletion src/hal/set_region_translate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -204,7 +204,7 @@ int xthal_v2p(void* vaddr, void** paddr, unsigned *way, unsigned* cattr) {
*way = iway;
if (paddr || cattr) {
unsigned temp;
unsigned ppn;
unsigned ppn = 0;
unsigned ppn1;
unsigned dtlbcfg = read_dtlbcfg();
temp = read_dtlb1_entry(probe);
Expand Down
476 changes: 476 additions & 0 deletions zephyr/soc/dc233c/xtensa/config/core-isa.h
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713 changes: 713 additions & 0 deletions zephyr/soc/dc233c/xtensa/config/core-matmap.h
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1 change: 0 additions & 1 deletion zephyr/soc/intel_s1000/xtensa/config/defs.h → zephyr/soc/dc233c/xtensa/config/defs.h
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Expand Up @@ -32,7 +32,6 @@

#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_misc.h>
#include <xtensa/tie/xt_booleans.h>

#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
26 changes: 15 additions & 11 deletions ...r/soc/intel_s1000/xtensa/config/specreg.h → zephyr/soc/dc233c/xtensa/config/specreg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
* Xtensa Special Register symbolic names
*/

/* $Id: //depot/rel/Homewood/ib.0/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
/* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */

/* Copyright (c) 1998-2002 Tensilica Inc.

Expand Down Expand Up @@ -37,21 +37,23 @@
#define LEND 1
#define LCOUNT 2
#define SAR 3
#define BR 4
#define LITBASE 5
#define SCOMPARE1 12
#define PREFCTL 40
#define ACCLO 16
#define ACCHI 17
#define MR_0 32
#define MR_1 33
#define MR_2 34
#define MR_3 35
#define WINDOWBASE 72
#define WINDOWSTART 73
#define PTEVADDR 83
#define RASID 90
#define ITLBCFG 91
#define DTLBCFG 92
#define IBREAKENABLE 96
#define MEMCTL 97
#define ATOMCTL 99
#define DDR 104
#define MEPC 106
#define MEPS 107
#define MESAVE 108
#define MESR 109
#define MECR 110
#define MEVADDR 111
#define IBREAKA_0 128
#define IBREAKA_1 129
#define DBREAKA_0 144
Expand Down Expand Up @@ -94,9 +96,11 @@
#define CCOMPARE_0 240
#define CCOMPARE_1 241
#define CCOMPARE_2 242

#define MISC_REG_0 244
#define MISC_REG_1 245

/* Special cases (bases of special register series): */
#define MR 32
#define IBREAKA 128
#define DBREAKA 144
#define DBREAKC 160
Expand Down
132 changes: 65 additions & 67 deletions ...yr/soc/intel_s1000/xtensa/config/system.h → zephyr/soc/dc233c/xtensa/config/system.h
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Expand Up @@ -10,7 +10,7 @@
* core-specific but system independent.
*/

/* Copyright (c) 2000-2010 Tensilica Inc.
/* Copyright (c) 2000-2007 Tensilica Inc.

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
Expand All @@ -35,31 +35,34 @@
#ifndef XTENSA_CONFIG_SYSTEM_H
#define XTENSA_CONFIG_SYSTEM_H

/*#include <xtensa/hal.h>*/



/*----------------------------------------------------------------------
CONFIGURED SOFTWARE OPTIONS
----------------------------------------------------------------------*/

#define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */

#define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */
/* The above maps to one of the following constants: */
#define XTHAL_ABI_WINDOWED 0
#define XTHAL_ABI_CALL0 1
/* Alternatives: */
/*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */
/*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */

#define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */
/* The above maps to one of the following constants: */
#define XTHAL_CLIB_NEWLIB 0
#define XTHAL_CLIB_UCLIBC 1
#define XTHAL_CLIB_XCLIB 2
/* Alternatives: */
/*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */
/*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */

#define XSHAL_USE_FLOATING_POINT 1

#define XSHAL_FLOATING_POINT_ABI 0

/* SW workarounds enabled for HW errata: */

/*----------------------------------------------------------------------
DEVICE ADDRESSES
----------------------------------------------------------------------*/
Expand All @@ -72,31 +75,31 @@
*/

/* I/O Block areas: */
#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000
#define XSHAL_IOBLOCK_CACHED_VADDR 0x30000000
#define XSHAL_IOBLOCK_CACHED_PADDR 0x30000000
#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000

#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000
#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000

/* System ROM: */
#define XSHAL_ROM_VADDR 0xBEFE0000
#define XSHAL_ROM_PADDR 0xBEFE0000
#define XSHAL_ROM_SIZE 0x00020000
#define XSHAL_ROM_VADDR 0xEE000000
#define XSHAL_ROM_PADDR 0xFE000000
#define XSHAL_ROM_SIZE 0x01000000
/* Largest available area (free of vectors): */
#define XSHAL_ROM_AVAIL_VADDR 0xBEFE0BC0
#define XSHAL_ROM_AVAIL_VSIZE 0x0001F440
#define XSHAL_ROM_AVAIL_VADDR 0xFE000300
#define XSHAL_ROM_AVAIL_VSIZE 0x00FFFD00

/* System RAM: */
#define XSHAL_RAM_VADDR 0x80000000
#define XSHAL_RAM_PADDR 0x80000000
#define XSHAL_RAM_VSIZE 0x3EFE0000
#define XSHAL_RAM_PSIZE 0x3EFE0000
#define XSHAL_RAM_VADDR 0xD0000000
#define XSHAL_RAM_PADDR 0x00000000
#define XSHAL_RAM_VSIZE 0x04000000
#define XSHAL_RAM_PSIZE 0x04000000
#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
/* Largest available area (free of vectors): */
#define XSHAL_RAM_AVAIL_VADDR 0x80000000
#define XSHAL_RAM_AVAIL_VSIZE 0x3EFE0000
#define XSHAL_RAM_AVAIL_VADDR 0x00002500
#define XSHAL_RAM_AVAIL_VSIZE 0x03FFDB00

/*
* Shadow system RAM (same device as system RAM, at different address).
Expand All @@ -107,25 +110,21 @@
* addresses are viewed through the BYPASS static map rather than
* the CACHED static map.
*/
#define XSHAL_RAM_BYPASS_VADDR 0x20000000
#define XSHAL_RAM_BYPASS_PADDR 0x20000000
#define XSHAL_RAM_BYPASS_PSIZE 0x20000000
#define XSHAL_RAM_BYPASS_VADDR 0x40000000
#define XSHAL_RAM_BYPASS_PADDR 0x40000000
#define XSHAL_RAM_BYPASS_PSIZE 0x04000000

/* Alternate system RAM (different device than system RAM): */
/*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/
/*#define XSHAL_ALTRAM_SIZE ...not configured...*/

/* Some available location in which to place devices in a simulation (eg. XTMP): */
#define XSHAL_SIMIO_CACHED_VADDR 0xC0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000
#define XSHAL_SIMIO_PADDR 0xC0000000
#define XSHAL_SIMIO_CACHED_VADDR 0xA0000000
#define XSHAL_SIMIO_BYPASS_VADDR 0xA0000000
#define XSHAL_SIMIO_PADDR 0xA0000000
#define XSHAL_SIMIO_SIZE 0x20000000


/*----------------------------------------------------------------------
* For use by reference testbench exit and diagnostic routines.
*/
#define XSHAL_MAGIC_EXIT 0xc0000000
#define XSHAL_STL_INFO_LOCATION 0x64

/*----------------------------------------------------------------------
* DEVICE-ADDRESS DEPENDENT...
*
Expand Down Expand Up @@ -153,26 +152,26 @@
* system (PIF) ROM, local memory, or XLMI. */

/* These set any unused 512MB region to cache-BYPASS attribute: */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22442222 /* enable caches in write-back mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22112222 /* enable caches in write-allocate mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22112222 /* enable caches in write-through mode */
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x77333333 /* enable caches in write-back mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0xBB333333 /* enable caches in write-allocate mode */
#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0xBB333333 /* enable caches in write-through mode */
#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x33333333 /* disable caches in bypass mode */
#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */

/* These set any unused 512MB region to ILLEGAL attribute: */
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFF44FFFF /* enable caches in write-back mode */
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFF11FFFF /* enable caches in write-through mode */
#define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */
#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0x77CCCCCC /* enable caches in write-back mode */
#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xBBCCCCCC /* enable caches in write-allocate mode */
#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xBBCCCCCC /* enable caches in write-through mode */
#define XSHAL_STRICT_CACHEATTR_BYPASS 0x33CCCCCC /* disable caches in bypass mode */
#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */

/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch
* NULL-pointer dereference bugs; all other unused 512MB regions are set
* to cache-BYPASS attribute: */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2211222F /* enable caches in write-allocate mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211222F /* enable caches in write-through mode */
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x7733333C /* enable caches in write-back mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0xBB33333C /* enable caches in write-allocate mode */
#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0xBB33333C /* enable caches in write-through mode */
#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x3333333C /* disable caches in bypass mode */
#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */

/*----------------------------------------------------------------------
Expand Down Expand Up @@ -200,26 +199,24 @@
* of whether the macro is _WRITEBACK vs. _BYPASS etc. */

/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF424F2F /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF121F2F /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF121F2F /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF222F2F /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x37CCC37C /* enable caches in write-back mode */
#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x3BCCC3BC /* enable caches in write-allocate mode */
#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x3BCCC3BC /* enable caches in write-through mode */
#define XSHAL_XT2000_CACHEATTR_BYPASS 0x33CCC33C /* disable caches in bypass mode */
#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */

#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000104 /* BusInt SDRAM regions */
#define XSHAL_XT2000_SDRAM_REGIONS 0x00000011 /* BusInt SDRAM regions */


/*----------------------------------------------------------------------
VECTOR INFO AND SIZES
----------------------------------------------------------------------*/

#define XSHAL_VECTORS_PACKED 0 /* UNUSED */
#define XSHAL_VECTORS_PACKED 0
#define XSHAL_STATIC_VECTOR_SELECT 0
#define XSHAL_RESET_VECTOR_VADDR 0xBEFE0000
#define XSHAL_RESET_VECTOR_PADDR 0xBEFE0000
#define XSHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400
#define XSHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400
#define XSHAL_RESET_VECTOR_VADDR 0xFE000000
#define XSHAL_RESET_VECTOR_PADDR 0xFE000000

/*
* Sizes allocated to vectors by the system (memory map) configuration.
Expand All @@ -233,32 +230,33 @@
#define XSHAL_RESET_VECTOR_SIZE 0x00000300
#define XSHAL_RESET_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_SIZE 0x00000038
#define XSHAL_USER_VECTOR_ISROM 1
#define XSHAL_USER_VECTOR_ISROM 0
#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNEL_VECTOR_SIZE 0x00000038
#define XSHAL_KERNEL_VECTOR_ISROM 1
#define XSHAL_KERNEL_VECTOR_ISROM 0
#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 1
#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000140
#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178
#define XSHAL_WINDOW_VECTORS_ISROM 1
#define XSHAL_WINDOW_VECTORS_ISROM 0
#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL2_VECTOR_ISROM 1
#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL3_VECTOR_ISROM 1
#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
#define XSHAL_INTLEVEL4_VECTOR_ISROM 0
#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL5_VECTOR_ISROM 1
#define XSHAL_INTLEVEL5_VECTOR_ISROM 0
#define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038
#define XSHAL_INTLEVEL6_VECTOR_ISROM 1
#define XSHAL_INTLEVEL6_VECTOR_ISROM 0
#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE
#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM
#define XSHAL_NMI_VECTOR_SIZE 0x00000038
#define XSHAL_NMI_VECTOR_ISROM 1
#define XSHAL_NMI_VECTOR_ISROM 0
#define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE


#endif /*XTENSA_CONFIG_SYSTEM_H*/

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